公开(公告)号：WO1994015359A1

公开(公告)日：1994-07-07

申请号：PCT/US1992011068

申请日：1992-12-18

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  SCHRANTZ, Gregory, A. ,  GAUL, Stephen, J.

IPC: H01L21/70

CPC classification number: H01L21/3226 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76275 ,  H01L21/76283 ,  H01L27/1203

Abstract: An integrated circuit structure containing dielectrically isolated islands having heat dissipation paths of enhanced thermal conductivity. A semiconductor structure comprises a first layer of crystalline material with a layer comprising polycrystalline diamond formed over the first layer. A layer of polycrystalline silicon is formed over the diamond containing layer and a layer of monocrystalline material is formed over the polycrystalline silicon.

Abstract translation: 包含具有增强导热性的散热路径的介电隔离岛的集成电路结构。 半导体结构包括第一层结晶材料，其中包含在第一层上形成的多晶金刚石层。 在含金刚石层上形成多晶硅层，并在多晶硅上形成一层单晶材料。

公开(公告)号：WO1993019486A1

公开(公告)日：1993-09-30

申请号：PCT/US1993002530

申请日：1993-03-19

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  GAUL, Stephen, Joseph ,  HEMMENWAY, Donald, Frank

IPC: H01L21/76

CPC classification number: H01L21/32 ,  H01L21/763

Abstract: A process of manufacturing a trench-isolated semiconductor structure comprises forming a first 'pad' (e.g. MOS gate) oxide layer on a first surface of a silicon substrate. An oxide etch protective layer of silicon nitride is selectively formed on a first portion of the pad oxide layer so as to overlie a first surface portion of the silicon substrate in which active device regions will be introduced. A second oxide layer is then deposited on the pad oxide layer and on the nitride layer. The dual oxide layer is then patterned to form a trench mask which exposes a second surface portion of the silicon substrate. An etchant is then applied to the structure so as to etch away material from the silicon substrate exposed by the second surface portion and a portion of the second oxide layer, thereby forming a trench in the second surface portion of the silicon substrate. After any remaining portion of the second oxide layer is removed, local oxidation of the structure is perfomed so as to form a third oxide layer in the trench and a field oxide at surface portions of the substrate adjacent to the nitride layer. A layer of polysilicon is non-selectively deposited over the entire structure to fill the oxide-lined trench and then polished down to the nitride layer which serves as a polishing stop. The nitride is then stripped off the pad oxide in preparation for device region processing.

公开(公告)号：WO1993011624A1

公开(公告)日：1993-06-10

申请号：PCT/US1992010379

申请日：1992-12-02

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  FAITH, Richard, William ,  LESTER, James, William

IPC: H04M03/02

CPC classification number: H04M19/023 ,  H02M5/297

Abstract: A frequency conversion circuit includes four analog switching elements (46, 48, 52, 54) coupled. Each switching element is logic controlled to open or close, i.e., to have either a high or low conductivity to pass or block analog currents of either polarity. Effectively, a signal received on the dual input (40, 42) may be enabled in inverted or non-inverted form onto the dual output (60, 62), depending on the control of the switches. The circuit may be used for producing a telephone ringing signal from an AC input signal. The circuit is coupled to receive an AC input signal, such as a 60 Hz signal derived from AC line power. The switching elements are alternately opened and closed during a predetermined sequence of half-cycles of the AC input signal. The circuit produces an output signal having a sequence of consecutive positive half-cycles and a sequence of consecutive negative half-cycles. Each switching element preferably includes a MOSFET switch stage providing either high or low impedance between two switch electrodes, a current amplifier (76, 78) for providing a gate voltage to the MOSFET switch stage, and a storage circuit including a capacitor (102) for storing energy while the switching element is open.

Abstract translation: 频率转换电路包括耦合的四个模拟开关元件（46,48,52,54）。 每个开关元件被逻辑控制以打开或关闭，即具有高或低电导率以通过或阻挡任一极性的模拟电流。 有效地，取决于开关的控制，在双输入（40,42）上接收的信号可以以反相或非反相的形式被启用到双输出（60,62）上。 电路可以用于从AC输入信号产生电话振铃信号。 电路被耦合以接收AC输入信号，例如从AC线路功率得到的60Hz信号。 开关元件在AC输入信号的半周期的预定顺序期间交替地打开和关闭。 该电路产生具有连续正半周期序列和连续负半周期序列的输出信号。 每个开关元件优选地包括在两个开关电极之间提供高阻抗或低阻抗的MOSFET开关级，用于向MOSFET开关级提供栅极电压的电流放大器（76,78），以及包括电容器（102）的存储电路， 在切换元件打开时存储能量。

公开(公告)号：WO1993009599A2

公开(公告)日：1993-05-13

申请号：PCT/US1992009366

申请日：1992-10-29

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  BACRANIA, Kantilal ,  CHI, Cong, In ,  CHURCH, Michael, David ,  COTREAU, Gerald, M. ,  DEJONG, Glenn, Alan ,  FISHER, Gregory, James ,  GASNER, John, Thomas ,  ITO, Akira ,  JOHNSTON, Jeffrey, Michael ,  KING, Ken, Richard ,  KUTCHMARICK, David ,  RHEE, Choong-Sun ,  RIEMER, David, Wayne

IPC: H03K05/15

CPC classification number: G05F3/267 ,  G05F3/262 ,  G05F3/30 ,  G11C27/026 ,  H01L21/8249 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/0688 ,  H03F1/523 ,  H03F3/505 ,  H03F2200/294 ,  H03G1/0082 ,  H03K5/15 ,  H03K17/223 ,  H03M1/162 ,  H03M1/365

Abstract: A two-step analog-to-digital converter (300) and BiCMOS fabrication method to make the converter. The fabrication method provides pseudosubstrate isolation of digital CMOS devices from analog devices. The converter uses NPN current switching in a flash analog-to-digital converter (306) and in a digital-to-analog converter (310) for low noise operation. CMOS digital error correction (318) and BiCMOS output drivers (320) provide high packing density plus large output load handling. Timing control (330) aggregates switching events and puts them into intervals when noise sensitive operations are inactive. The fabrication method uses a thin epitaxial layer with limited thermal processing to provide NPN and PNP devices with large breakdown and Early voltages. Laser trimmed resistors provide small-long term drift due to dopant stabilization in underlying BPSG and low hydrogen nitride passivation.

Abstract translation: 一种两步模拟数字转换器（300）和BiCMOS制造方法来制造转换器。 该制造方法提供了数字CMOS器件与模拟器件的伪衬底隔离。 该转换器在闪存模数转换器（306）和数模转换器（310）中使用NPN电流切换用于低噪声操作。 CMOS数字纠错（318）和BiCMOS输出驱动器（320）提供高封装密度和大输出负载处理。 定时控制（330）聚合切换事件，并在噪声敏感操作无效时将其置于间隔。 该制造方法使用具有有限热处理的薄外延层来为NPN和PNP器件提供大的击穿和早期电压。 激光微调电阻由于底层BPSG和低氮化氢钝化中的掺杂剂稳定性而提供小的长期漂移。

公开(公告)号：WO1993007678A1

公开(公告)日：1993-04-15

申请号：PCT/US1992008735

申请日：1992-10-13

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  JOHNSTONE, William, Franklin ,  DAMEROW, David, Henry

IPC: H03H17/06

CPC classification number: H03H17/0276 ,  H03H17/0664 ,  H03H17/0685

Abstract: Decimation circuitry is provided having a forward shifting data section (14) receiving data samples in order including a plurality of forward decimation registers (17-20) coupled in-line and providing a forward register output. Each forward decimation register operates as a FIFO register having a decimation depth. A backward shifting data section (16) includes a plurality of backward decimation registers (21-23) having a decimation depth coupled in-line and providing a backward register output. One of the backward decimation registers (24) which receives data samples in sequence form one of the forward decimation registers can function as both a LIFO and a FIFO register, when a LIFO register, it operates to reverse blocks of data samples wherein the size of each block corresponds to the decimation rate. Each reversed block is then shifted through the backward shifting data section. Each of the other backward decimation registers operates as FIFO register. The decimation circuitry can be used to form a digital filter cascadable into various sizes.

公开(公告)号：WO1993006681A1

公开(公告)日：1993-04-01

申请号：PCT/US1992007964

申请日：1992-09-18

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  PARKER, Geoffrey, H. ,  HEFLEY, Andrew, J.

IPC: H04M09/08

CPC classification number: H04M1/24 ,  H04M1/6033 ,  H04M3/30

Abstract: A telephone test set that performs dry loop testing of telephone lines has a passive speech network, a speakerphone circuit, and an amplifier and a speaker coupled to the speakerphone circuit. The passive speech network and the speakerphone circuit area isolated by the use of latching relays which are switched by a relay driver circuit that provides a short current burst. Line power can be used to power the speakerphone, so as to extend battery life of a battery which can augment the line power as needed.

Abstract translation: 执行电话线的干环测试的电话测试机具有被动语音网络，扬声器电路，以及耦合到扬声器电路的放大器和扬声器。 被动语音网络和扬声器电路区域通过使用由提供短电流脉冲串的继电器驱动电路切换的闭锁继电器隔离。 线路电源可用于为扬声器供电，从而延长电池的电池寿命，可根据需要增加线路电源。

公开(公告)号：WO1993003547A1

公开(公告)日：1993-02-18

申请号：PCT/US1992006511

申请日：1992-08-05

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  SNOW, Dane, Roderick

IPC: H03M01/52

CPC classification number: H03M1/52

Abstract: An improved integrating type A/D converter has a set of analog switches and a control logic unit for selectively connecting a pair of input terminals for an unknown analog input voltage signal with a pair of input leads across a buffer and integrator in order to apply, first in an integrate phase, the analog input signal in a polarity direction that causes the integrator to ramp up in the same direction regardless of the polarity of the analog input signal, and then in a deintegrate phase, reference voltages are applied across the input leads in a direction opposite to the ramp-up direction of the integrator such that a zero crossing signal is output by the comparator. The ramping-up and ramping-down of the integrator in the same direction eliminates rollover error in the A/D reading of inputs of different polarities but of the same magnitude. The invention is particularly useful for monolithic A/D converters using BiMOS technology. The preferred embodiment performs a subdivided measurement of a number of integrate/deintegrate phases of the analog input signal, and a second, residual error measurement using a pair of storage capacitors with capacitances in a predetermined multiplier ratio.

公开(公告)号：WO1992022820A3

公开(公告)日：1992-12-23

申请号：PCT/US1992005109

申请日：1992-06-12

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  BEITMAN, Bruce, A.

IPC: G01P15/08

公开(公告)号：WO1992019009A1

公开(公告)日：1992-10-29

申请号：PCT/US1992003354

申请日：1992-04-23

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  LIPPITT, Maxwell, W., III

IPC: H01L21/268

CPC classification number: H01L21/76889 ,  H01L21/76894 ,  Y10S148/093 ,  Y10S438/94

Abstract: A method including covering the area to be laser trimmed with a first insulative layer (22) having a thickness sufficiently thin that a layer can trim the area through the first insulative layer. An etch stop (26) is formed on the first insulative layer over the aera to be trimmed and covered with a second insulative layer (28). A portion of the second insulative layer is etched to expose the etch stop and a portion of the etch stop is then removed to expose a portion of the first insulative layer and laser trimming is conducted through the exposed first insulative layer. The etch stop is part of a first level of interconnects (24) made of the same material and simultaneously with the etch stop. The area to be trimmed is part of a second level of contacts that interconnect another second material.

公开(公告)号：WO1992017977A1

公开(公告)日：1992-10-15

申请号：PCT/US1992002688

申请日：1992-04-03

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  KENNEDY, Michael ,  PIERCE, Ben ,  CHAN, Aaron

IPC: H04M03/30

CPC classification number: H04M3/30

Abstract: A remotely controlled line conditioning apparatus (80) is installed in the terminal (12) where access to the telephone loop (52) to be tested is readily available. The line conditioning apparatus (80) includes a telephone line termination unit (100) and an intelligent control unit (110). The telephone line termination unit has a telephone line access port to which a telephone line pair is selectively coupled, and is operative to controllably impart a selected one of a plurality of electrical signalling conditions to the telephone line pair under test. The control unit has a communication modem (112) through which communication signals containing telephone line conditioning messages are coupled to and from the central office/remote terminal communication link. The control unit also includes a micro-controller (122). Control signals generated by the micro-controller control the operation of the telephone line termination unit which conditions the telephone line pair.