公开(公告)号：WO1998026572A3

公开(公告)日：1998-06-18

申请号：PCT/IB1997001661

申请日：1997-12-12

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  WALKER, Herbert, M.

IPC: H04M19/02

公开(公告)号：WO1998016007A1

公开(公告)日：1998-04-16

申请号：PCT/US1997018309

申请日：1997-10-08

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  SUCHOFF, Michael ,  BARBER, Andrew, C.

IPC: H03H17/02

CPC classification number: H03H17/0223 ,  H03H17/06

Abstract: A reduced hardware complexity, reduced computational intensity finite impulse response filter architecture for filtering multiple (quadrature) channels of an RF modem comprises a cascaded arrangement of L data register stages through which respective digitally encoded data sample values of a signal to be filtered are sequentially clocked. Each data register stage has a data capacity greater than twice the code width of a respective digitized channel sample, so that each register stage can store both I and Q channel data. A multiplier unit is coupled to the data register and multiplies both I and Q contents of respective ones of the register stages by respective impulse response coefficient values. The resulting I and Q products are summed into I and Q channel convolutional sums.

Abstract translation: 降低的硬件复杂度，降低的计算强度有限脉冲响应滤波器架构用于对RF调制解调器的多个（正交）信道进行滤波，包括L个数据寄存器级的级联布置，通过该L个数据寄存器级将要被滤波的信号的相应的数字编码数据采样值顺序地被定时 。 每个数据寄存器级的数据容量大于相应数字化通道样本的代码宽度的两倍，因此每个寄存器级都可以存储I和Q通道数据。 乘法器单元耦合到数据寄存器，并通过相应的脉冲响应系数值将寄存器级中的各个寄存器级的I和Q内容相乘。 所得到的I和Q产品被归结为I和Q通道卷积和。

公开(公告)号：WO1998000959A2

公开(公告)日：1998-01-08

申请号：PCT/US1997011509

申请日：1997-06-30

Applicant: HARRIS CORPORATION ,  JACKSON, Allen, Lee ,  HOCHMAN, David, Charles ,  SIKAND, Parminder, Singh ,  PETERSEN, Charles, Louis ,  TERHUNE, Daniel, Scott ,  UKENO, Richard

Inventor： HARRIS CORPORATION

IPC: H04M03/42

CPC classification number: H04M3/436 ,  H04M3/42102 ,  H04M3/42229 ,  H04M3/465 ,  H04M3/54 ,  H04M2242/22 ,  H04Q3/72

Abstract: A method for routing a call to a called party who may be located at any one of plural sites which avoids delays in connecting the called party to the received call. When a call is received at a switch, a controller at the switch uses an embedded data base to identify plural sites where the called party may be located from among a multiplicity of sites to which the switch can be connected and causes the switch to initiate parallel connections from the switch to the identified sites. Another method of operating a telephone system in which a called party receives a telephone call from a calling party which is not to be answered and in which the called party is free to use its telephone while continuing to provide a ring signal to the calling party. Upon receipt of one or more rings at the called party's telephone, one or more key strokes are entered at the called party's telephone to provide a refusal signal to the telephone system which is providing a ring signal to the calling party. A further method of routing an incoming telephone call to a called party having plural telephone numbers in which a telephone call for the called party is received at a switching system, and automatically screened to determine where the received call is to be routed among plural devices with different telephone numbers for accessing the called party, where the devices may include a wireless telephone and a pager.

Abstract translation: 本发明提供了一种用于在几个位置中的任何一个位置向用户发送呼叫的方法，同时避免了将接收到的呼叫发送给被叫用户的延迟。 当交换机接收到呼叫时，交换机级控制器实施一个嵌入式数据库，以从交换机可能连接的多个站点中识别可以到达被叫用户的多个站点。 并使交换机在交换机和识别的站点之间同时建立连接。 本发明涉及另一种操作电话网络的方法，其中被叫用户从呼叫者接收到预期不会响应的呼叫，被叫用户能够在继续他的呼叫的同时自由地使用他的电话。 向主叫方发送呼叫信号。 在他的电话上接收到一个或多个呼叫之后，用户点击他的电话上的一个或多个键以发送拒绝信号给发送呼叫信号给呼叫者的电话网络。 本发明还涉及用于向具有几个电话号码的被叫用户发送在交换系统上接收到的输入通信的另一种方法。 自动分析来话通信以确定具有不同电话号码的几个设备中的哪个设备将接收的呼叫路由到被叫用户，这些设备可以是无线电话或移动电话。 接听电话的人。

公开(公告)号：WO1997001235A2

公开(公告)日：1997-01-09

申请号：PCT/US1996010333

申请日：1996-06-13

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  BARRON, Joseph, Eugene ,  SCHILLACI, Onofrio

IPC: H04M00/00

CPC classification number: H04Q11/045 ,  H04M3/303

Abstract: A subscriber line circuit test arrangement for a non-metallic (fiber optic) digital communication path-based digital communication network that employs a single (basic rate ISDN) metallic channel unit (BMCU) installed at a site terminating the fiber optic communication path. A BMCU communicates with a central office test system using an auxiliary B-ISDN communication 'test' channel portion (2B+D) of the time division multiplexed digital communication DS0 channels. Digital command and response signals are transported by the two ISDN bearer (B) channels and are coupled directly to tip and ring digital signal processors in the central office test system. The data (D) channel is employed to conduct access, calibration and control communications with the metallic channel unit.

Abstract translation: 一种用于非金属（光纤）数字通信路径的数字通信网络的用户线电路测试装置，其使用安装在终止光纤通信路径的站点处的单个（基本速率ISDN）金属信道单元（BMCU）。 BMCU使用时分复用数字通信DS0信道的辅助B-ISDN通信“测试”信道部分（2B + D）与中心局测试系统进行通信。 数字命令和响应信号由两个ISDN载体（B）信道传输，并直接耦合到中心局测试系统中的尖端和环形数字信号处理器。 采用数据（D）通道进行与金属通道单元的通信，校准和控制通信。

公开(公告)号：WO1995015008A1

公开(公告)日：1995-06-01

申请号：PCT/US1994013566

申请日：1994-11-23

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  NEILSON, John, Manning, Savidge ,  WHEATLEY, Carl, Franklin, Jr. ,  JONES, Frederick, Peter ,  TEMPLE, Victor, Albert, Keith

IPC: H01L29/78

CPC classification number: H01L29/7802 ,  H01L29/0696 ,  Y10S148/126

Abstract: A pattern for a wafer for a MOS-gated semiconductor device includes plural ribbons extending from a source contact region to another source contact region, each of the ribbons having a single source region between two channel regions, so as to increase the device's current-carrying capability per unit area relative to the prior art. The pattern increases the size of the active current-carrying area (the channel and neck regions of the device) relative to the area of the source contact areas. The source contact regions may be discrete or linear, and the ribbons may extend therefrom perpendicularly or at other angles.

Abstract translation: 用于MOS门控半导体器件的晶片的图案包括从源极接触区域延伸到另一个源极接触区域的多个带，每个带子在两个沟道区域之间具有单个源极区域，以便增加器件的载流 相对于现有技术的每单位面积的能力。 该图案相对于源接触区域的面积增加了有效载流区域（器件的通道和颈部区域）的尺寸。 源极接触区可以是离散的或线性的，并且带可以从其垂直地或以其它角度延伸。

公开(公告)号：WO1994005037A1

公开(公告)日：1994-03-03

申请号：PCT/US1993008017

申请日：1993-08-26

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  BAJOR, George ,  RIVOLI, Anthony, L.

IPC: H01L21/76

CPC classification number: H01L21/302 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/763

Abstract: Recessed isolation oxide is deposited in shallow trenches simultaneously with oxide deposition in deep isolation trenches. A single planarization of both trench fillings provides efficient recessed isolation oxide without bird's beak or bird's head problems of LOCOS isolation oxide. Self-aligned trench filling by successive conformal depositions of oxide and polysilicon followed by planarization to remove polysilicon away from the trenches. The remaining polysilicon may be used as an oxide etch mask to remove all of the oxide except in the trenches.

Abstract translation: 嵌入的隔离氧化物沉积在浅沟槽中，同时具有深度隔离沟槽中的氧化物沉积。 两个沟槽填充物的单一平面化提供了有效的凹陷隔离氧化物，而没有鸟嘴或LOCOS隔离氧化物的鸟头问题。 通过氧化物和多晶硅的连续共形沉积的自对准沟槽填充，随后进行平面化以从沟槽移除多晶硅。 剩余的多晶硅可以用作氧化物蚀刻掩模以除去除了沟槽中的所有氧化物。

公开(公告)号：WO1994003928A1

公开(公告)日：1994-02-17

申请号：PCT/US1992006780

申请日：1992-08-06

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  CROFT, Gregg, D.

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L27/0251 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/12032 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A high voltage protection circuit includes breakdown networks for providing a discharge path between a pair of terminals of a circuit to be protected. Each network conducts current between a supply terminal and another terminal at a low threshold voltage value when power is removed from the supply terminal. The network increases the threshold value when power is applied to the supply terminal to prevent conduction through the breakdown network during normal operation of the circuit to be protected. In one implementation, the protection circuit includes anti-latching circuitry connected to the breakdown network for preventing the breakdown network from latching on after or during the time power is applied to the supply terminals. To minimize the degradation of DC operating characteristics, the leakage currents, due to the protection circuit, between the first terminal and the positive supply terminal, and between the first terminal and the negative supply terminal cancel each other. The protection circuit may be incorporated on the same substrate as the circuit to be protected or it may be incorporated on a separate substrate sharing a common housing with the circuit to be protected. Alternately, the protection circuit may be in its own housing with its external leads connected to the leads of a first housing including the circuit to be protected.

Abstract translation: 高压保护电路包括用于在要保护的电路的一对端子之间提供放电路径的击穿网络。 当电源从供电端子移除时，每个网络以低阈值电压值在电源端子和另一个端子之间传导电流。 当电源施加到供电端子时，网络增加阈值，以防止在要保护的电路的正常工作期间通过击穿网络导通。 在一个实施方式中，保护电路包括连接到击穿网络的防闩锁电路，用于防止击穿网络在向电源端子施加电力之后或期间锁定。 为了最小化直流工作特性的劣化，由于第一端子和正电源端子之间以及第一端子和负电源端子之间的保护电路引起的漏电流彼此抵消。 保护电路可以被结合在与要保护的电路相同的衬底上，或者可以将其与被保护电路共用共用外壳的单独衬底上。 或者，保护电路可以在其自己的壳体中，其外部引线连接到包括要保护的电路的第一壳体的引线。

公开(公告)号：WO1993013559A1

公开(公告)日：1993-07-08

申请号：PCT/US1992010974

申请日：1992-12-18

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  TEMPLE, Victor, Albert, Keith ,  ARTHUR, Stephen, D.

IPC: H01L29/72

CPC classification number: H01L29/7455 ,  H01L29/749

Abstract: A composite thyristor comprising a plurality of parallel connected identical thyristor cells (40) each of the cells including a turn-on field effect transistor (FET) (72) and a turn-off FET (62). The gate electrodes (34) of all the FETs form a grid-like pattern on a surface of the semiconductor substrate of the device. The pattern includes strips which intersect at corners. Turn-off FETs (62) are formed along the boundary of the grid and beneath it, and turn-on FETs (72) are disposed beneath the corners.

公开(公告)号：WO1993013554A1

公开(公告)日：1993-07-08

申请号：PCT/US1992011102

申请日：1992-12-18

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  BEASOM, James, D.

IPC: H01L21/76

CPC classification number: H01L29/407 ,  H01L21/763 ,  H01L29/0808 ,  H01L29/735

Abstract: The tendency of mobile positive ions to be transported into device regions of a bipolar transistor is effectively minimized by surrounding the transistor with a "positive ion"-attracting electric field, preferably by applying a prescribed bias to the fill material of a conductive trench that surrounds the device. The trench which surrounds a respective device to be protected contains dielectric material disposed along sidewalls of the trench. The trench contains material such as undoped polysilicon, which is capable of distributing a voltage, so that the material in the trench is insulated by dielectric material from an adjacent portion of the semiconductor substrate surrounded by the trench. In order to prevent mobile positive ions from moving into a device region in response to temperature bias stress and thereby degrade an operational parameter of the transistor, a predefined (relatively negative) bias voltage is applied to the material in the trench. By relatively negative is meant that the magnitude of the predefined bias voltage is established to be no more positive than half the difference between the most positive and the most negative of bias voltages that are applied to the device. Preferably, the prescribed bias voltage corresponds to the most negative of the plurality of bias voltages of the transistor.

Abstract translation: 通过用“正离子”吸收电场围绕晶体管，可以有效地将移动正离子传输到双极晶体管的器件区域的趋势最小化，优选地通过向环绕的导电沟槽的填充材料施加规定的偏压 装置。 围绕待保护的相应装置的沟槽包含沿着沟槽的侧壁设置的介电材料。 沟槽包含诸如未掺杂多晶硅的材料，其能够分配电压，使得沟槽中的材料由电介质材料与由沟槽围绕的半导体衬底的相邻部分绝缘。 为了防止移动正离子响应于温度偏压应力而进入器件区域，从而降低晶体管的工作参数，将预定的（相对负的）偏置电压施加到沟槽中的材料。 相对负的意思是，预定义的偏置电压的幅度被建立为不超过施加到器件的偏置电压的最正和最负的差的一半。 优选地，规定的偏置电压对应于晶体管的多个偏置电压中最负的。

公开(公告)号：WO1993011567A1

公开(公告)日：1993-06-10

申请号：PCT/US1992010094

申请日：1992-11-23

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  NEILSON, John, Manning, Savidge

IPC: H01L29/76

CPC classification number: H01L29/7802 ,  H01L23/585 ,  H01L29/0615 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7395 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power FET composed of a substrate having upper and lower surfaces and having at least one body region (2) of a first conductivity type which extends to said upper surface (4); and at least one base region (6) extending into the substrate from the upper surface, the base region being of a second conductivity type and having at least two portions between which the at least one body region extends, and an insulated gate (20) disposed at the upper surface above the body region, the substrate further has a shielding region (30) of the second conductivity type extending into the least one body region from the upper surface, at a location below the gate electrode and enclosed by the base region portions, and spaced from the base region by parts of the body region of the first conductivity type.

Abstract translation: 一种功率FET，由具有上表面和下表面的基板组成，并具有延伸到所述上表面（4）的至少一个第一导电类型的体区（2）; 以及从上表面延伸到基底中的至少一个基底区域（6），所述基底区域是第二导电类型并且具有至少两个部分，所述至少两个部分之间至少一个体区域延伸，以及绝缘栅极（20） 所述基板设置在所述主体区域上方的上表面，所述基板还具有从所述上表面延伸到所述至少一个体区域中的所述第二导电类型的屏蔽区域，所述屏蔽区域在所述栅电极下方的位置被所述基极区域包围 部分，并且与第一导电类型的身体区域的一部分与基部区域隔开。