公开(公告)号：US20160378672A1

公开(公告)日：2016-12-29

申请号：US14752783

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Subramanya R. Dulloor ,  Rajesh M. Sankaran ,  Sanjay Kumar

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/214 ,  G06F2212/7201

Abstract: Hardware apparatuses and methods for distributed durable and atomic transactions in non-volatile memory are described. In one embodiment, a hardware apparatus includes a hardware processor, a plurality of hardware memory controllers for each of a plurality of non-volatile data storage devices, and a plurality of staging buffers with a staging buffer for each of the plurality of hardware memory controllers, wherein each of the plurality of hardware memory controllers are to: write data of a data set that is to be written to the plurality of non-volatile data storage devices to their staging buffer, send confirmation to the hardware processor that the data is written to their staging buffer, and write the data from their staging buffer to their non-volatile data storage device on receipt of a commit command.

Abstract translation: 描述了在非易失性存储器中用于分布式持久和原子事务的硬件装置和方法。 在一个实施例中，硬件设备包括硬件处理器，用于多个非易失性数据存储设备中的每一个的多个硬件存储器控制器，以及多个具有用于多个硬件存储器控制器中的每一个的暂存缓冲器的登台缓冲器 其中，所述多个硬件存储器控制器中的每一个要将要写入所述多个非易失性数据存储装置的数据组的数据写入其暂存缓冲器，向所述硬件处理器发送所述数据被写入的确认 并且在接收到提交命令时将数据从其暂存缓冲区写入其非易失性数据存储设备。

公开(公告)号：US09423959B2

公开(公告)日：2016-08-23

申请号：US13931875

申请日：2013-06-29

Applicant: Intel Corporation

Inventor： Subramanya R. Dulloor ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Gilbert Neiger ,  Richard A. Uhlig ,  Robert S. Chappell ,  Joseph Nuzman ,  Kai Cheng ,  Sailesh Kottapalli ,  Yen-Cheng Liu ,  Mohan Kumar ,  Raj K. Ramanujan ,  Glenn J. Hinton

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0671 ,  G06F13/1668

Abstract: An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.

Abstract translation: 描述了用于在持久存储器架构中的存储耐久性和排序的装置和方法。 例如，方法的一个实施例包括：对识别至少一个持久存储器设备的一个或多个地址执行至少一个存储操作，所述存储操作使一个或多个存储器控制器将数据存储在所述至少一个持久存储器设备中; 向所述一个或多个存储器控制器发送请求消息，指示所述存储器控制器确认所述存储操作被成功地提交给所述至少一个持久存储器设备; 确保在所述一个或多个存储器控制器处，至少在请求消息时接收到的所有未决存储操作将被提交给持久存储器设备; 以及从所述一个或多个存储器控制器发送指示所述存储操作被成功地提交给所述持久存储器设备的响应消息。

公开(公告)号：US09262338B1

公开(公告)日：2016-02-16

申请号：US14675292

申请日：2015-03-31

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A. Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US20250103397A1

公开(公告)日：2025-03-27

申请号：US18401399

申请日：2023-12-30

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Daniel Joe ,  Filip Schmole ,  Philip Abraham ,  Stephen R. Van Doren ,  Priya Autee ,  Rajesh M. Sankaran ,  Anthony Luck ,  Philip Lantz ,  Eric Wehage ,  Edwin Verplanke ,  James Coleman ,  Scott Oehrlein ,  David M. Lee ,  Lee Albion ,  David Harriman ,  Vinit Mathew Abraham ,  Yi-Feng Liu ,  Manjula Peddireddy ,  Robert G. Blankenship

IPC: G06F9/50

Abstract: Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a processing device includes execution circuitry to execute a plurality of software threads; hardware to control monitoring or allocating, among the plurality of software threads, one or more shared resources; and configuration storage to enable the monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more channels through which one or more devices are to be connected to the one or more shared resources.

公开(公告)号：US20240338319A1

公开(公告)日：2024-10-10

申请号：US18745603

申请日：2024-06-17

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Philip R. Lantz ,  Ashok Raj ,  Kun Tian

IPC: G06F12/1009 ,  G06F9/455 ,  G06F12/06 ,  G06F12/1081

CPC classification number: G06F12/1009 ,  G06F9/45558 ,  G06F12/063 ,  G06F12/1081 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2009/45591

Abstract: Embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. In an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (PASID) to locate a PASID-entry. The context entry is to include at least one of a page-table pointer to a page-table translation structure and a PASID. The PASID-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure. The PASID is to be supplied by the device. At least one of the apparatus, the context entry, and the PASID entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.

公开(公告)号：US20240289160A1

公开(公告)日：2024-08-29

申请号：US18658822

申请日：2024-05-08

Applicant: Intel Corporation

Inventor： Barry E. Huntley ,  Jr-Shian Tsai ,  Gilbert Neiger ,  Rajesh M. Sankaran ,  Mesut A. Ergin ,  Ravi L. Sahita ,  Andrew J. Herdrich ,  Wei Wang

IPC: G06F9/455 ,  G06F9/30 ,  G06F12/02 ,  G06F12/10 ,  G06F12/109 ,  G11C7/10

CPC classification number: G06F9/45558 ,  G06F9/3004 ,  G06F9/45533 ,  G06F12/0292 ,  G06F12/10 ,  G06F12/109 ,  G11C7/1072 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2009/45595 ,  G06F2212/151

Abstract: A processor of an aspect includes a decode unit to decode an aperture access instruction, and an execution unit coupled with the decode unit. The execution unit, in response to the aperture access instruction, is to read a host physical memory address, which is to be associated with an aperture that is to be in system memory, from an access protected structure, and access data within the aperture at a host physical memory address that is not to be obtained through address translation. Other processors are also disclosed, as are methods, systems, and machine-readable medium storing aperture access instructions.

公开(公告)号：US12045185B2

公开(公告)日：2024-07-23

申请号：US18296875

申请日：2023-04-06

Applicant: Intel Corporation

Inventor： Philip R. Lantz ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Saurabh Gayen

IPC: G06F13/364 ,  G06F9/50 ,  G06F13/24

CPC classification number: G06F13/364 ,  G06F9/5027 ,  G06F13/24

Abstract: Embodiments of apparatuses, methods, and systems for highly scalable accelerators are described. In an embodiment, an apparatus includes an interface to receive a plurality of work requests from a plurality of clients and a plurality of engines to perform the plurality of work requests. The work requests are to be dispatched to the plurality of engines from a plurality of work queues. The work queues are to store a work descriptor per work request. Each work descriptor is to include all information needed to perform a corresponding work request.

公开(公告)号：US11656899B2

公开(公告)日：2023-05-23

申请号：US17404897

申请日：2021-08-17

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Rajesh M. Sankaran ,  Gilbert Neiger ,  Philip R. Lantz ,  Jason W. Brandt ,  Vedvyas Shanbhogue ,  Utkarsh Y. Kakaiya ,  Kun Tian

IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1045 ,  G06F12/109

CPC classification number: G06F9/45558 ,  G06F9/30138 ,  G06F12/109 ,  G06F12/1063 ,  G06F2009/45579 ,  G06F2212/152

Abstract: Implementations of the disclosure provide a processing device comprising an address translation circuit to intercept a work request from an I/O device. The work request comprises a first ASID to map to a work queue. A second ASID of a host is allocated for the first ASID based on the work queue. The second ASID is allocated to at least one of: an ASID register for a dedicated work queue (DWQ) or an ASID translation table for a shared work queue (SWQ). Responsive to receiving a work submission from the SVM client to the I/O device, the first ASID of the application container is translated to the second ASID of the host machine for submission to the I/O device using at least one of: the ASID register for the DWQ or the ASID translation table for the SWQ based on the work queue associated with the I/O device.

公开(公告)号：US20230134657A1

公开(公告)日：2023-05-04

申请号：US17519384

申请日：2021-11-04

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Philip R. Lantz ,  Rajesh M. Sankaran ,  Gilbert Neiger ,  Rupin H. Vakharwala

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/54 ,  G06F13/24

Abstract: A system comprises a physical processor to execute a virtual machine manager to run, on a logical core, a virtual machine including a guest user application and a virtual CPU. Circuitry coupled to an external device is to receive an interrupt request from the external device for the guest user application, locate a first interrupt data structure associated with the guest user application, generate a first interrupt with the first interrupt data structure based on a first interrupt vector for the interrupt request, locate a second interrupt data structure associated with the virtual CPU, and generate a first notification interrupt for the virtual CPU with the second interrupt data structure based on a first notification vector in the first interrupt data structure. The circuitry may generate a second notification interrupt for the logical core using a second notification vector and a logical core identifier from the second interrupt data structure.

公开(公告)号：US20230032586A1

公开(公告)日：2023-02-02

申请号：US17711928

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Narayan Ranganathan ,  Philip R. Lantz ,  Rajesh M. Sankaran ,  Sanjay Kumar ,  Saurabh Gayen ,  Nikhil Rao ,  Utkarsh Y. Kakaiya ,  Dhananjay A. Joshi ,  David Jiang ,  Ashok Raj

IPC: G06F3/06 ,  G06F9/455

Abstract: Methods and apparatus relating to scalable access control checking for cross-address-space data movement are described. In an embodiment, a memory stores an InterDomain Permissions Table (IDPT) having a plurality of entries. At least one entry of the IDPT provides a relationship between a target address space identifier and a plurality of requester address space identifiers. A hardware accelerator device allows access to a target address space, corresponding to the target address space identifier, by one or more of requesters, corresponding to the plurality of requester address space identifiers, respectively, based at least in part on the relationship provided by the at least one entry of the IDPT. Other embodiments are also disclosed and claimed.