公开(公告)号：US12292842B2

公开(公告)日：2025-05-06

申请号：US17486579

申请日：2021-09-27

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Anjali Jain ,  Reshma Lal ,  Edwin Verplanke ,  Priya Autee ,  Chih-Jen Chang ,  Abhirupa Layek ,  Nupur Jain

IPC: G06F13/38 ,  G06F13/16 ,  G06F13/28 ,  H04L45/02 ,  H04L45/64 ,  H04L67/289 ,  H04L69/321

Abstract: Examples described herein relate to network layer 7 (L7) offload to an infrastructure processing unit (IPU) for a service mesh. An apparatus described herein includes an IPU comprising an IPU memory to store a routing table for a service mesh, the routing table to map shared memory address spaces of the IPU and a host device executing one or more microservices, wherein the service mesh provides an infrastructure layer for the one or more microservices executing on the host device; and one or more IPU cores communicably coupled to the IPU memory, the one or more IPU cores to: host a network L7 proxy endpoint for the service mesh, and communicate messages between the network L7 proxy endpoint and an L7 interface device of the one or more microservices by copying data between the shared memory address spaces of the IPU and the host device based on the routing table.

公开(公告)号：US12197601B2

公开(公告)日：2025-01-14

申请号：US17560193

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Ren Wang ,  Sameh Gobriel ,  Somnath Paul ,  Yipeng Wang ,  Priya Autee ,  Abhirupa Layek ,  Shaman Narayana ,  Edwin Verplanke ,  Mrittika Ganguli ,  Jr-Shian Tsai ,  Anton Sorokin ,  Suvadeep Banerjee ,  Abhijit Davare ,  Desmond Kirkpatrick ,  Rajesh M. Sankaran ,  Jaykant B. Timbadiya ,  Sriram Kabisthalam Muthukumar ,  Narayan Ranganathan ,  Nalini Murari ,  Brinda Ganesh ,  Nilesh Jain

IPC: G06F15/78 ,  G06F9/50 ,  G06F21/62 ,  G06F21/72

Abstract: Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.

公开(公告)号：US11520700B2

公开(公告)日：2022-12-06

申请号：US17042037

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Iosif Gasparakis ,  Sunku Ranganath ,  Liyong Qiao ,  Rui Zang ,  Dakshina Ilangovan ,  Shaohe Feng ,  Edwin Verplanke ,  Priya Autee ,  Lin A. Yang

IPC: G06F12/08 ,  G06F9/50 ,  G06F9/54 ,  G06F12/0806

Abstract: A holistic view of cache class of service (CLOS) to include an allocation of processor cache resources to a plurality of CLOS. The allocation of processor cache resources to include allocation of cache ways for an n-way set of associative cache. Examples include monitoring usage of the plurality of CLOS to determine processor cache resource usage and to report the processor cache resource usage.

公开(公告)号：US12271308B2

公开(公告)日：2025-04-08

申请号：US18399553

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Priya Autee ,  Abhishek Khade ,  Patrick Lu ,  Edwin Verplanke ,  Vivekananthan Sanjeepan

IPC: G06F12/0802

Abstract: Examples provide an application program interface or manner of negotiating locking or pinning or unlocking or unpinning of a cache region by which an application, software, or hardware. A cache region can be part of a level-1, level-2, lower or last level cache (LLC), or translation lookaside buffer (TLB) are locked (e.g., pinned) or unlocked (e.g., unpinned). A cache lock controller can respond to a request to lock or unlock a region of cache or TLB by indicating that the request is successful or not successful. If a request is not successful, the controller can provide feedback indicating one or more aspects of the request that are not permitted. The application, software, or hardware can submit another request, a modified request, based on the feedback to attempt to lock a portion of the cache or TLB.

公开(公告)号：US12066939B2

公开(公告)日：2024-08-20

申请号：US17086243

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Rahul R. Shah ,  Omkar Maslekar ,  Priya Autee ,  Edwin Verplanke ,  Andrew J. Herdrich ,  Jeffrey D. Chamberlain

IPC: G06F12/00 ,  G06F9/30 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/1009

CPC classification number: G06F12/0811 ,  G06F9/30047 ,  G06F9/30079 ,  G06F12/084 ,  G06F12/1009

Abstract: Examples described herein relate to a manner of demoting multiple cache lines to shared memory. In some examples, a shared cache is accessible by at least two processor cores and a region of the cache is larger than a cache line and is designated for demotion from the cache to the shared cache. In some examples, the cache line corresponds to a memory address in a region of memory. In some examples, an indication that the region of memory is associated with a cache line demote operation is provided in an indicator in a page table entry (PTE). In some examples, the indication that the region of memory is associated with a cache line demote operation is based on a command in an application executed by a processor. In some examples, the cache is an level 1 (L1) or level 2 (L2) cache.

公开(公告)号：US20250103397A1

公开(公告)日：2025-03-27

申请号：US18401399

申请日：2023-12-30

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Daniel Joe ,  Filip Schmole ,  Philip Abraham ,  Stephen R. Van Doren ,  Priya Autee ,  Rajesh M. Sankaran ,  Anthony Luck ,  Philip Lantz ,  Eric Wehage ,  Edwin Verplanke ,  James Coleman ,  Scott Oehrlein ,  David M. Lee ,  Lee Albion ,  David Harriman ,  Vinit Mathew Abraham ,  Yi-Feng Liu ,  Manjula Peddireddy ,  Robert G. Blankenship

IPC: G06F9/50

Abstract: Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a processing device includes execution circuitry to execute a plurality of software threads; hardware to control monitoring or allocating, among the plurality of software threads, one or more shared resources; and configuration storage to enable the monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more channels through which one or more devices are to be connected to the one or more shared resources.

公开(公告)号：US12235761B2

公开(公告)日：2025-02-25

申请号：US16514226

申请日：2019-07-17

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Priya Autee ,  Abhishek Khade ,  Patrick Lu ,  Edwin Verplanke ,  Vivekananthan Sanjeepan

IPC: G06F12/0802

Abstract: Examples provide an application program interface or manner of negotiating locking or pinning or unlocking or unpinning of a cache region by which an application, software, or hardware. A cache region can be part of a level-1, level-2, lower or last level cache (LLC), or translation lookaside buffer (TLB) are locked (e.g., pinned) or unlocked (e.g., unpinned). A cache lock controller can respond to a request to lock or unlock a region of cache or TLB by indicating that the request is successful or not successful. If a request is not successful, the controller can provide feedback indicating one or more aspects of the request that are not permitted. The application, software, or hardware can submit another request, a modified request, based on the feedback to attempt to lock a portion of the cache or TLB.

公开(公告)号：US20240330053A1

公开(公告)日：2024-10-03

申请号：US18194408

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Philip Abraham ,  Priya Autee ,  Stephen Van Doren ,  Yen-Cheng Liu ,  Rajesh Sankaran ,  Kameswar Subramaniam ,  Ritesh Parikh

IPC: G06F9/50 ,  G06F9/30

CPC classification number: G06F9/5016 ,  G06F9/3009 ,  G06F9/5044

Abstract: Techniques for region-aware memory bandwidth allocation control are described. In an embodiment, an apparatus includes a processing core and control circuitry. The processing core is to execute a plurality of threads. The control circuitry is to control use of memory bandwidth per memory region and per thread.

公开(公告)号：US20220014459A1

公开(公告)日：2022-01-13

申请号：US17486579

申请日：2021-09-27

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Anjali Jain ,  Reshma Lal ,  Edwin Verplanke ,  Priya Autee ,  Chih-Jen Chang ,  Abhirupa Layek ,  Nupur Jain

IPC: H04L12/751 ,  H04L12/715 ,  G06F13/28 ,  G06F13/16

Abstract: Examples described herein relate to network layer 7 (L7) offload to an infrastructure processing unit (IPU) for a service mesh. An apparatus described herein includes an IPU comprising an IPU memory to store a routing table for a service mesh, the routing table to map shared memory address spaces of the IPU and a host device executing one or more microservices, wherein the service mesh provides an infrastructure layer for the one or more microservices executing on the host device; and one or more IPU cores communicably coupled to the IPU memory, the one or more IPU cores to: host a network L7 proxy endpoint for the service mesh, and communicate messages between the network L7 proxy endpoint and an L7 interface device of the one or more microservices by copying data between the shared memory address spaces of the IPU and the host device based on the routing table.