公开(公告)号：US09728580B2

公开(公告)日：2017-08-08

申请号：US13892600

申请日：2013-05-13

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Steffen Thiele

IPC: G01K7/01 ,  H01L27/16

CPC classification number: H01L27/16 ,  G01K7/01

Abstract: A power transistor has a semiconductor body with a bottom side and top side spaced distant from the bottom side in a vertical direction. The semiconductor body includes a plurality of transistor cells, a source zone of a first conduction type, a body zone of a second conduction type, a drift zone of the first conduction type, a drain zone, and a temperature sensor diode having a pn-junction between an n-doped cathode zone and a p-doped anode zone. The power transistor also has a drain contact terminal on the top side, a source contact terminal on the bottom side, a gate contact terminal, and a temperature sense contact terminal on the top side. Depending on the first and second conduction types the anode or cathode zone is electrically connected to the source contact terminal and the other diode zone is electrically connected to the temperature sense contact terminal.

公开(公告)号：US20170213783A1

公开(公告)日：2017-07-27

申请号：US15414815

申请日：2017-01-25

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Matthias Grewe ,  Stefan Macheiner

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49562 ,  H01L23/49524 ,  H01L23/49575 ,  H01L23/49593 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/376 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2224/37599

Abstract: A semiconductor package is disclosed. The semiconductor package includes an electrically conducting carrier having a mounting surface, a first level first semiconductor power device having a first load electrode mounted over the mounting surface of the electrically conducting carrier and having a second load electrode opposite the first electrode. The package further includes a first level second semiconductor power device. A first connection element has a first surface connected to the second load electrode of the first level first semiconductor power device. A second connection element has a first surface connected to the second load electrode of the first level second semiconductor power device. The package includes a second level first semiconductor power device and a second level second semiconductor power device.

公开(公告)号：US20170162660A1

公开(公告)日：2017-06-08

申请号：US15437932

申请日：2017-02-21

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/417 ,  H01L27/15 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/4175 ,  H01L21/2255 ,  H01L21/26586 ,  H01L27/156 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/7835

Abstract: A semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region, and the gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction, the body region being adjacent to the source region and the drain region. The semiconductor device further comprises a source contact and a body contact, the source contact being electrically connected to a source terminal, the body contact being electrically connected to the source contact and to the body region.

公开(公告)号：US09661707B2

公开(公告)日：2017-05-23

申请号：US15138739

申请日：2016-04-26

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/66 ,  H05B33/08 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L27/092

CPC classification number: H05B33/083 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/78

Abstract: A semiconductor device includes first and second field effect transistors (FETs) formed in a semiconductor substrate having a first main surface. The first FET includes first source and drain contact grooves, each running in a first direction parallel to the first main surface, each formed in the first main surface. First source regions are electrically connected to a conductive material in the first source contact groove. First drain regions are electrically connected to a conductive material in the first drain contact groove. The second FET includes second source and drain contact grooves, each running in a second direction parallel to the first main surface, each formed in the first main surface. Second source regions are electrically connected to a conductive material in the second source contact groove, and second drain regions are electrically connected to a conductive material in the second drain contact groove.

公开(公告)号：US20170117383A1

公开(公告)日：2017-04-27

申请号：US15398818

申请日：2017-01-05

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Anton Mauder ,  Markus Zundel ,  Hans-Joachim Schulze ,  Franz Hirler ,  Hans Weber

IPC: H01L29/66 ,  H01L21/306 ,  H01L29/78 ,  H01L29/06 ,  H01L29/739 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L29/66333 ,  H01L21/02118 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/30604 ,  H01L21/76831 ,  H01L21/76898 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/402 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/861

Abstract: A method for forming a semiconductor device includes forming an electrical structure at a main surface of a semiconductor substrate and carrying out an anodic oxidation of a back side surface region of a back side surface of the semiconductor substrate to form an oxide layer at the back side surface of the semiconductor substrate. Additionally, the method includes connecting a carrier substrate to the oxide layer and processing a back side of the semiconductor substrate.

公开(公告)号：US09614032B2

公开(公告)日：2017-04-04

申请号：US15081423

申请日：2016-03-25

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/45 ,  H01L21/265 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/0634 ,  H01L21/26586 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1008 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7825

Abstract: A semiconductor device comprises a transistor in a semiconductor body having a first main surface and a second main surface, the first main surface being opposite to the second main surface. The transistor comprises a source region at the first main surface, a drain region, a body region, a drift zone, and a gate electrode at the body region. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The gate electrode is disposed in trenches extending in the first direction. The transistor further comprises an insulating layer adjacent to the second main surface of the body region. The source region vertically extends to the second main surface.

公开(公告)号：US20170033189A1

公开(公告)日：2017-02-02

申请号：US15220794

申请日：2016-07-27

Applicant: Infineon Technologies AG

Inventor： Wolfgang Werner ,  Peter lrsigler ,  Andreas Meiser

IPC: H01L29/40 ,  H01L29/423 ,  H01L21/308 ,  H01L21/765 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/407 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/76224 ,  H01L21/765 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66234 ,  H01L29/66666 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/73 ,  H01L29/7825 ,  H01L29/7827

Abstract: A method of manufacturing a structure in a semiconductor body comprises forming a first mask above a first surface of the semiconductor body. The first mask comprises an opening surrounding a first portion of the first mask, thereby separating the first portion and a second portion of the first mask. The semiconductor body is processed through the opening at the first surface. The opening is increased by removing at least part of the first mask in the first portion while maintaining the first mask in the second portion. The semiconductor body is further processed through the opening at the first surface.

Abstract translation: 一种制造半导体器件中的结构的方法包括在半导体本体的第一表面之上形成第一掩模。 第一掩模包括围绕第一掩模的第一部分的开口，从而分离第一掩模的第一部分和第二部分。 通过第一表面处的开口处理半导体本体。 通过在第一部分中移除第一掩模的至少一部分同时将第一掩模保持在第二部分中来增加开口。 半导体本体通过第一表面处的开口被进一步加工。

公开(公告)号：US20160365443A1

公开(公告)日：2016-12-15

申请号：US15182120

申请日：2016-06-14

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7819 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

Abstract: A transistor cell includes a drift region, a source region, a body region, and a drain region that is laterally spaced apart from the source region. A gate electrode is adjacent the body region. A field electrode is arranged in the drift region. A source electrode is connected to the source region and the body region, and a drain electrode is connected to the drain region. An avalanche bypass structure is coupled between the source electrode and the drain electrode and includes a first semiconductor layer of the first doping type, a second semiconductor layer of the first doping type, and a pn-junction arranged between the first semiconductor layer and the source electrode. The second semiconductor layer has a higher doping concentration than the first semiconductor layer and is arranged between the second semiconductor layer and the drift region. The drain electrode is electrically connected to the second semiconductor layer.

Abstract translation: 晶体管单元包括与源极区域横向间隔开的漂移区域，源极区域，体区域和漏极区域。 栅电极与身体区域相邻。 场漂移区域设置场电极。 源电极连接到源极区域和主体区域，并且漏电极连接到漏极区域。 雪崩旁路结构耦合在源电极和漏极之间，并且包括第一掺杂型的第一半导体层，第一掺杂型的第二半导体层和布置在第一半导体层和源极之间的pn结 电极。 第二半导体层具有比第一半导体层更高的掺杂浓度，并且布置在第二半导体层和漂移区之间。 漏极电连接到第二半导体层。

公开(公告)号：US20160197070A1

公开(公告)日：2016-07-07

申请号：US15051105

申请日：2016-02-23

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andreas Meiser ,  Hans-Peter Lang ,  Thorsten Meyer ,  Peter Irsigler

IPC: H01L27/06 ,  H01L29/45 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/861

CPC classification number: H01L29/7813 ,  H01L21/02 ,  H01L21/743 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/48 ,  H01L27/0629 ,  H01L27/0694 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7803 ,  H01L29/7827 ,  H01L29/7845 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor body having first and second opposing sides. Contact trenches extend, from the first and second sides, through a dielectric and into the semiconductor body. The contact trenches include conductive material electrically connected to the semiconductor body via sidewalls. The contact trenches include a first contact trench extending through a first dielectric and into the semiconductor body at the first side, the first contact trench including a first conductive material electrically connected to the semiconductor body adjoining the first contact trench, a second contact trench extending through a second dielectric and into the semiconductor body at the second side, the second contact trench including a second conductive material, a first contact pattern surrounded by the first dielectric at the first side, and a second contact pattern surrounded by the second dielectric at the second side.

Abstract translation: 半导体器件包括具有第一和第二相对侧的半导体本体。 接触沟槽从第一侧和第二侧延伸穿过电介质并进入半导体本体。 接触沟槽包括通过侧壁电连接到半导体本体的导电材料。 接触沟槽包括延伸穿过第一电介质并在第一侧进入半导体本体的第一接触沟槽，第一接触沟槽包括电连接到邻接第一接触沟槽的半导体本体的第一导电材料，延伸穿过第二接触沟槽 第二电介质并且在第二侧进入半导体本体，第二接触沟槽包括第二导电材料，由第一侧面处的第一电介质围绕的第一接触图案和在第二侧被第二电介质包围的第二接触图案 侧。

公开(公告)号：US20160190256A1

公开(公告)日：2016-06-30

申请号：US15062370

申请日：2016-03-07

Applicant: Infineon Technologies AG

Inventor： Martin Vielemeyer ,  Andreas Meiser ,  Till Schloesser ,  Franz Hirler ,  Martin Poelzl

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7825

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.

Abstract translation: 半导体器件包括具有主表面的半导体衬底中的晶体管。 晶体管包括源极区，漏极区，沟道区，漂移区，栅电极和与栅电极相邻的栅极电介质。 栅电极设置成与沟道区域的至少两侧相邻。 沟道区域和漂移区域沿着平行于源极区域和漏极区域之间的主表面的第一方向设置。 栅极电介质具有在栅电极的不同位置处变化的厚度。