公开(公告)号：WO1998028839A1

公开(公告)日：1998-07-02

申请号：PCT/US1997023449

申请日：1997-12-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  OVARD, David, K. ,  PAX, George, E.

IPC: H03D03/00

CPC classification number: H04L1/06 ,  H04L27/2332

Abstract: A differentially phase shift keyed demodulator (52) for use in an interrogator of a remote intelligent communication system. The demodulator includes a quadrature combiner (64) delaying one of the quadrature signals and thereafter combining the delayed and undelayed signals along with a FIR matched filter (66), which filters the combiner output whereby the differentially phase shift keyed data on a sub-carrier can be demodulated using a simple delay and multiplying scheme (68, 70) in response to the filtered output.

Abstract translation: 一种用于远程智能通信系统的询问器的差分相移键控解调器（52）。 解调器包括延迟正交信号之一的正交组合器（64），之后将延迟和未延迟的信号与FIR匹配滤波器（66）组合，其对组合器输出进行滤波，从而在子载波上差分相移键控数据 可以使用简单的延迟和乘法方案（68,70）响应于滤波的输出来解调。

公开(公告)号：WO1998025345A1

公开(公告)日：1998-06-11

申请号：PCT/US1997022001

申请日：1997-12-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  KEETH, Brent

IPC: H03K05/00

CPC classification number: G11C7/225 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/06

Abstract: An integrated circuit, such as a memory integrated circuit, includes a vernier clock adjustment circuit receiving an input clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay. An edge triggered circuit receives data and the rising-edge and falling-edge clock signals, and stores data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal. One form of the invention is a memory system having a memory controller coupled to memory modules through data and commande busses. Each memory module includes the vernier clock adjustment circuitry.

Abstract translation: 诸如存储器集成电路的集成电路包括接收输入时钟信号并提供表示延迟了上升沿延迟的输入时钟信号的上升沿时钟信号的游标时钟调整电路，并提供下降沿时钟信号 表示延迟了下降沿延迟的输入时钟信号。 边沿触发电路接收数据和上升沿和下降沿时钟信号，并将数据存储在上升沿时钟信号的上升沿和下降沿时钟信号的下降沿。 本发明的一种形式是具有通过数据和命令总线与存储器模块耦合的存储器控​​制器的存储器系统。 每个存储器模块包括游标时钟调整电路。

公开(公告)号：WO1998024184A1

公开(公告)日：1998-06-04

申请号：PCT/US1997022167

申请日：1997-11-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  KEETH, Brent

IPC: H03K19/003

CPC classification number: H03K19/018585 ,  H03K19/00361

Abstract: An output driver circuit offers wave-shaping and logic level adjustment for high speed data communications in a synchronous memory such as a dynamic random access memory (DRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Wave-shaping functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtain different wave-shaping characteristics of the output signal.

Abstract translation: 输出驱动器电路为诸如动态随机存取存储器（DRAM）的同步存储器中的高速数据通信提供波形整形和逻辑电平调整。 通过端接电阻之间的电阻分压和输出节点与VDD和VSS电源之间的可控阻抗获得电平调整。 波形整形功能包括响应于输入信号中的转变顺序地导通或关闭输出晶体管，在输出节点处的信号的转换速率修改。 输出晶体管的不同加权方案获得输出信号的不同波形整形特性。

公开(公告)号：WO1998020554A1

公开(公告)日：1998-05-14

申请号：PCT/US1996017685

申请日：1996-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  VANNORTWICK, John ,  CLIFFORD, Scott

IPC: H01L23/495

CPC classification number: H01L23/4951 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/83101 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method and apparatus for cutting and applying adhesive tape to a lead frame for a lead-on-chip (LOC) semiconductor package are provided. The method includes indexing double sided adhesive tape (54) into a guide opening, and then moving a tape cutter (52) through the guide opening (50) to cut the tape into a decal (74) having finished dimension equal to the width of the tape (54). The finished dimension can be either the width or length of the decal (74). In either case the decal (74) is formed with only two cut edges and no wasted tape (54). The tape cutter (52) in addition to cutting the tape (54) also presses the cut decal (74) against the lead frame (42); a pair of tape feed rollers (46, 48) for indexing the tape (54); a tape guide (50) for guiding and positioning the tape for cutting; and a tape cutter assembly (52) for cutting and pressing the cut decal (74) against the lead frame (12). The tape cutter assembly (52) includes the guide opening (50) and a tape cutter adapted to move through the guide opening.

Abstract translation: 提供了一种将粘合带切割并施加到用于片上芯片（LOC）半导体封装的引线框架的方法和装置。 该方法包括将双面胶带（54）分成导向开口，然后通过导向开口（50）移动带式切割器（52），以将带切割成具有等于宽度 带（54）。 完成的尺寸可以是贴花的宽度或长度（74）。 在任一情况下，贴花（74）仅形成两个切割边缘，并且没有浪费的带（54）。 除了切割带（54）之外，带切割器（52）还将切割的贴花（74）压靠在引线框架（42）上; 一对用于分度带（54）的送带辊（46,48）; 用于引导和定位用于切割的带的带引导件（50） 以及用于将切割的贴花（74）切割并压靠在引线框架（12）上的带切割器组件（52）。 带切割器组件（52）包括引导开口（50）和适于移动穿过引导开口的带切割器。

公开(公告)号：WO1998014998A1

公开(公告)日：1998-04-09

申请号：PCT/US1997017970

申请日：1997-10-03

Applicant: MICRON TECHNOLOGY, INC. ,  HEMBREE, David, R.

Inventor： MICRON TECHNOLOGY, INC.

IPC: H01L21/66

CPC classification number: H01L23/32 ,  G01R1/0483 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A temporary package for testing semiconductor dice, a method for forming the temporary package and a method for testing dice using the temporary package are provided. The temporary package (14) includes hard-metal ball contacts (38) arranged in a dense grid pattern, such as a ball grid array. The dense grip pattern allows the temporary package to include a large number of ball contacts (e.g., 50 to 1000 or more) to permit testing of a die (12) having a large number of bond pads or input/output signals. The ball contacts can be formed of a metal such as nickel, copper or beryllium copper and are adapted to resist wear, deformation and breakage during continued use of the package. For forming the package, a package base can be formed with land pads and the ball contacts can be attached to the land pads by soldering, brazing, welding, or with a conductive adhesive.

Abstract translation: 提供了用于测试半导体裸片的临时封装，用于形成临时封装的方法和使用临时封装测试管芯的方法。 临时包装（14）包括布置成致密栅格图案的硬金属球接触件（38），例如球栅阵列。 紧密抓握图案允许临时包装包括大量的球接触件（例如，50至1000或更多），以允许对具有大量接合焊盘或输入/输出信号的管芯（12）进行测试。 球接触件可以由诸如镍，铜或铍铜的金属形成，并且适于在继续使用包装期间抵抗磨损，变形和断裂。 为了形成封装，可以用焊盘形成封装基座，并且可以通过焊接，钎焊，焊接或用导电粘合剂将球接触件附接到焊盘焊盘。

公开(公告)号：WO1998014304A1

公开(公告)日：1998-04-09

申请号：PCT/US1997017679

申请日：1997-09-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  DOAN, Trung, Tri ,  MEIKLE, Scott, G.

IPC: B24B37/04

CPC classification number: B24B37/26 ,  B24D11/00 ,  Y10S451/921

Abstract: A polishing pad (42) for use in chemical-mechanical planarization (CMP) of semiconductor wafers includes a multiplicity of elongated microcolumns (48) embedded in a matrix material body (44). The elongated microcolumns (48) are oriented parallel to each other and extend from a planarizing surface used to planarize the semiconductor wafers. The elongated microcolumns (48) are uniformly distributed throughout the polishing pad (42) in order to impart uniform properties throughout the polishing pad (42). The polishing pad can also include elongated pores (50) either coaxial with or interspersed between the elongated microcolumns (48) to provide uniform porosity throughout the polishing pad (42).

Abstract translation: 用于半导体晶片的化学机械平面化（CMP）的抛光垫（42）包括嵌入基质材料体（44）中的多个细长微柱（48）。 细长的微柱（48）彼此平行定向并且从用于平坦化半导体晶片的平坦化表面延伸。 细长的微柱（48）均匀分布在整个抛光垫（42）中，以便在整个抛光垫（42）中赋予均匀的性能。 抛光垫还可以包括细长孔（50），其与细长微柱（48）同轴或分散在细孔中，以在整个抛光垫（42）中提供均匀的孔隙。

公开(公告)号：WO1998012706A1

公开(公告)日：1998-03-26

申请号：PCT/US1997014564

申请日：1997-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  FARNWORTH, Warren, M. ,  WARK, James, M. ,  NELSON, Eric, S. ,  DUESMAN, Kevin, G.

IPC: G11C29/00

CPC classification number: H01L22/22 ,  G01R31/2884 ,  G11C29/46 ,  G11C29/785 ,  G11C29/80 ,  G11C29/808 ,  H01L2224/48091 ,  H04J2203/0062 ,  H01L2924/00014

Abstract: An IC module (20), such as a Multi-Chip Module (MCM), includes multiple IC (12) dice each having a test mode enable bond pad (30), such as an output enable pad. A fuse incorporated into the MCM's substrate connects each dice's test mode enable pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable pads to one of the MCM's reference voltage pins. By applying a supply voltage to the test mode enable pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a reference voltage applied to the test mode enable pads through the reference voltage pins and the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging. A method for performing such testing once the test mode has been initiated and for repairing any failing elements found during testing, includes providing test signals to the dice, receiving response signals from the dice, evaluating the response signals to identify any failing elements in the dice, programming the failing elements addresses into anti-fuses in the dice with a programming voltage, confirming that the addresses are programmed by determining the resistance of the anti-fuses, re-testing the dice, receiving response signals from the re-tested dice, and evaluating the response signals to confirm all repairs.

Abstract translation: 诸如多芯片模块（MCM）的IC模块（20）包括多个具有测试模式使能接合焊盘（30）的IC（12）芯片，诸如输出使能焊盘。 集成到MCM基板中的保险丝将每个骰子的测试模式使能焊盘连接到MCM的无连接（N / C）引脚之一，并且连接到衬底中的电阻将测试模式使能焊盘连接到MCM的参考电压引脚之一 。 通过向测试模式使能焊盘通过N / C引脚施加电源电压，在骰子中启动测试模式。 一旦测试完成，保险丝可能会被熔断，并且施加到测试模式的参考电压使得焊盘能够通过参考电压引脚，并且电阻器将禁用骰子中的测试模式并启动操作模式。 因此，封装在IC模块中的裸片可以在封装后进行测试。 一旦测试模式已经启动并且用于修复在测试期间发现的任何故障元件，执行这种测试的方法包括向骰子提供测试信号，从骰子接收响应信号，评估响应信号以识别骰子中的任何故障元件 将故障元件地址编程为具有编程电压的骰子中的抗熔丝，通过确定抗熔丝的电阻，重新测试骰子，从重新测试的骰子接收响应信号来确认地址被编程， 并评估响应信号以确认所有维修。

公开(公告)号：WO1997049134A3

公开(公告)日：1997-12-24

申请号：PCT/US1997010591

申请日：1997-06-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  PRALL, Kirk, D.

IPC: H01L27/12

公开(公告)号：WO1997040498A1

公开(公告)日：1997-10-30

申请号：PCT/US1997006600

申请日：1997-04-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  SHIRLEY, Brian, M.

IPC: G11C07/00

CPC classification number: G11C11/4099 ,  G11C7/14 ,  G11C11/4085

Abstract: Tracking circuitry is described for use in a memory device. The tracking circuitry can be used to monitor word line voltages in a dynamic random access memory (DRAM) and includes a comparator circuit which compares a simulated word line signal to a digit line equilibrate bias voltage. The equilibrate bias voltage is generated using either memory column circuitry or a linear resistor voltage divider.

Abstract translation: 描述跟踪电路用于存储器件。 跟踪电路可以用于监视动态随机存取存储器（DRAM）中的字线电压，并且包括将模拟字线信号与数字线路平衡偏置电压进行比较的比较器电路。 使用存储器列电路或线性电阻分压器产生平衡偏置电压。

公开(公告)号：WO1997037383A1

公开(公告)日：1997-10-09

申请号：PCT/US1997005433

申请日：1997-04-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  FARNWORTH, Warren, M. ,  WOOD, Alan, G.

IPC: H01L23/28

CPC classification number: H01L24/06 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/525 ,  H01L24/02 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A process for making a semiconductor device and the resulting device having standardized die-to-substrate bonding locations are herein disclosed. The semiconductor die (32) provides a standard ball grid or other array of a particular size, pitch and pattern such that as the size, configuration or bond pad arrangement of the die changes, a standard substrate (60) (the term including leadrames) having a similarly standardized array of terminals (62, 64) or trace ends can be employed to form a semiconductor device (30). It is also contemplated that dies having markedly different circuitry but a common array pattern may be employed with the same substrate or other carrier.

Abstract translation: 本文公开了一种制造半导体器件的方法以及具有标准化管芯到衬底接合位置的所得器件。 半导体管芯（32）提供具有特定尺寸，间距和图案的标准球栅或其他阵列，使得随着管芯的尺寸，配置或焊盘排列的改变，标准衬底（该术语包括引线框架） 具有类似标准化的端子阵列（62,64）或迹线端可用于形成半导体器件（30）。 还可以设想，具有明显不同的电路但公共阵列图案的管芯可以与相同的衬底或其它载体一起使用。