公开(公告)号：WO1998029812A1

公开(公告)日：1998-07-09

申请号：PCT/US1997024207

申请日：1997-12-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  PAWLOWSKI, Joseph, Thomas

IPC: G06F12/08

CPC classification number: G06F12/0879

Abstract: A system and method of efficiently transferring a cache line of data between a cache memory to a processor. A first group of M words is transferred between the cache memory and the processor in a first cache transfer cycle, where the first group of M words includes a tag word and M-1 words from the plurality of data words in the cache line. A second group of M words is transferred between the cache memory and the processor in a second cache transfer cycle, where the second group of M words includes M additional words from the plurality of data words. The process continues until the entire cache line has been transferred between the cache memory and the processor.

Abstract translation: 一种在高速缓冲存储器与处理器之间高效地传输数据高速缓存行的系统和方法。 第一组M字在第一高速缓存传输周期中在高速缓冲存储器和处理器之间传送，其中第一组M字包括来自高速缓存行中的多个数据字的标签字和M-1个字。 第二组M字在第二高速缓存传送周期中在高速缓冲存储器和处理器之间传送，其中第二组M个字包括来自多个数据字的M个附加字。 该过程继续，直到整个高速缓存行已经在高速缓冲存储器和处理器之间传送。

公开(公告)号：WO1998014953A1

公开(公告)日：1998-04-09

申请号：PCT/US1997017985

申请日：1997-10-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  CASPER, Stephen, L. ,  MARTIN, Chris, G.

IPC: G11C17/18

CPC classification number: G11C17/18

Abstract: An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.

Abstract translation: 描述了使用锁存电路和两个反熔丝的反熔丝检测电路。 反熔丝耦合在锁存电路和地之间。 所描述的锁存电路是可以检测两个反熔丝中的哪一个已被编程的差分电路。 该电路精确检测在编程后具有较高电阻的反熔丝。

公开(公告)号：WO1998012707A1

公开(公告)日：1998-03-26

申请号：PCT/US1997016724

申请日：1997-09-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  ROBERTS, Gordon ,  MILER, James, E., Jr.

IPC: G11C29/00

CPC classification number: G06F11/2733 ,  G06F11/2273 ,  G11C29/48

Abstract: An integrated circuit includes an integrated circuit die mounted in a package having a plurality of externally accessible contacts. A functional circuit, such as a memory circuit, is formed on the integrated circuit die and is coupled through bonding pads to the external contacts of the integrated circuit. A test circuit is also formed on the integrated circuit die to allow performance parameters to be determined by performing tests on the test circuit when the test circuit is in wafer form before packaging. To allow tests to be performed on the test circuit after packaging, a switch circuit formed on the integrated circuit die selectively couples input/output terminals of the test circuit to respective bonding pads that are connected to the externally accessible contacts. The switch circuit is operated by a switch controller, which may be a decoder that responds to a pattern of signals or a sequence of signals applied to the externally accessible contacts or an overvoltage detector that responds to a voltage outside a range of operating voltages for the functional circuit.

Abstract translation: 集成电路包括安装在具有多个外部可访问触点的封装中的集成电路管芯。 诸如存储器电路的功能电路形成在集成电路管芯上，并且通过焊盘耦合到集成电路的外部触点。 在集成电路管芯上还形成一个测试电路，以便在封装前测试电路处于晶圆形式时，通过对测试电路进行测试来确定性能参数。 为了允许在封装之后在测试电路上执行测试，形成在集成电路管芯上的开关电路将测试电路的输入/输出端子选择性地耦合到连接到外部可访问触点的相应焊盘。 开关电路由开关控制器操作，开关控制器可以是响应于施加到外部可触摸触点的信号模式或信号序列的解码器，或过电压检测器，其响应于工作电压范围外的电压， 功能电路。

公开(公告)号：WO1998006102A1

公开(公告)日：1998-02-12

申请号：PCT/US1997013881

申请日：1997-08-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  CASPER, Stephen, L.

IPC: G11C17/18

CPC classification number: G11C17/18 ,  G11C7/067

Abstract: An antifuse detect circuit senses the conductance of a programmable element, such as an antifuse or fuse, and provides a logic output corresponding to the state of the programmable element. A capacitor precharges a comparator input above its input voltage trip point. The programmable element discharges the comparator input below the trip point depending upon its conductance state. The circuit allows quick and accurate sensing of the state of the programmable element, even when it is only marginally conductive, and improves reliability of the programmable element. The programmable element is used in remapping memory cells such as in a dynamic random access memory (DRAM). The state of the programmable element is sensed during precharging of addressing logic, and optionally latched when a row address strobe (RAS) signal is asserted.

Abstract translation: 反熔丝检测电路感测诸如反熔丝或熔丝的可编程元件的电导，并提供对应于可编程元件的状态的逻辑输出。 电容器将比较器输入预充电到其输入电压跳变点之上。 可编程元件根据其电导状态将比较器输入放电到触发点以下。 该电路允许对可编程元件的状态进行快速和准确的感测，即使只有稍微导通，并且提高了可编程元件的可靠性。 可编程元件用于重新映射存储器单元，例如在动态随机存取存储器（DRAM）中。 在寻址逻辑的预充电期间感测可编程元件的状态，并且当行地址选通（RAS）信号被断言时可选地被锁存。

公开(公告)号：WO1997050116A1

公开(公告)日：1997-12-31

申请号：PCT/US1997010574

申请日：1997-06-23

Applicant: MICRON TECHNOLOGY, INC. ,  GRAETTINGER, Thomas, M. ,  SCHUELE, Paul, J. ,  McCLURE, Brent

Inventor： MICRON TECHNOLOGY, INC.

IPC: H01L21/3205

CPC classification number: H01L27/10852 ,  H01L21/3205 ,  H01L28/55

Abstract: A method for forming a capacitor includes forming a substrate (30) having a node location to which electrical connection to a capacitor is to be made; forming an inner capacitor plate (60) over the node location, the inner capacitor plate having an exposed sidewall (61); forming an oxidation barrier layer (70) over the exposed inner capacitor plate sidewall; forming a capacitor dielectric plate (90) over the inner capacitor plate, the oxidation barrier layer restricting oxidation of the inner capacitor plate sidewall during formation of the capacitor dielectric plate; and forming an outer capacitor plate (100) over the capacitor dielectric plate. A capacitor is further described which includes an inner capacitor plate having at least one sidewall; an oxidation barrier layer positioned in covering relation to the at least one sidewall; a capacitor dielectric plate positioned over the inner capacitor plate; and an outer capacitor plate positioned over the capacitor dielectric plate. In the preferred form of the invention, an insulating dielectric layer (80) is positioned on the oxidation barrier layer (70), the insulating dielectric layer being of a different composition than the oxidation barrier layer.

Abstract translation: 形成电容器的方法包括：形成具有与电容器进行电连接的节点位置的衬底（30）; 在所述节点位置上形成内部电容器板（60），所述内部电容器板具有暴露的侧壁（61）; 在暴露的内部电容器板侧壁上形成氧化阻挡层（70）; 在所述内部电容器板上形成电容器电介质板，所述氧化阻挡层在形成所述电容器电介质板期间限制所述内部电容器侧壁的氧化; 以及在所述电容器电介质板上形成外部电容器板（100）。 进一步描述一种电容器，其包括具有至少一个侧壁的内部电容器板; 定位成覆盖所述至少一个侧壁的氧化阻挡层; 位于内部电容器板上的电容器电介质板; 以及位于电容器电介质板上的外部电容器板。 在本发明的优选形式中，绝缘电介质层（80）位于氧化阻挡层（70）上，绝缘电介质层具有与氧化阻挡层不同的组成。

公开(公告)号：WO1997036327A1

公开(公告)日：1997-10-02

申请号：PCT/US1997004660

申请日：1997-03-21

Applicant: MICRON TECHNOLOGY, INC. ,  DENNISON, Charles, H.

Inventor： MICRON TECHNOLOGY, INC.

IPC: H01L27/108

CPC classification number: H01L27/10852

Abstract: A semiconductor processing method of forming a contact pedestal includes: a) providing a node location (28) to which electrical connection is to be made; b) providing insulating dielectric material (30) over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a sufficient degree but not to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer (44) within the opening; f) etching through the contact opening base to outwardly expose the node location; g) filling the contact opening with an electrically conductive material (56); h) rendering the sidewall spacer electrically conductive.

Abstract translation: 形成接触基座的半导体处理方法包括：a）提供要进行电连接的节点位置（28）; b）在节点位置上提供绝缘电介质材料（30）; c）在足够程度上将接触开口蚀刻到所述节点位置上的所述绝缘介电材料中，但不能向外暴露所述节点位置，所述接触开口具有基部; d）在接触开口内的绝缘电介质材料上方设置间隔层，其厚度小于完全填充接触开口的厚度; e）各向异性蚀刻间隔层以在开口内形成侧壁间隔物（44）; f）通过接触开口底部蚀刻以向外暴露节点位置; g）用导电材料（56）填充接触开口; h）使侧壁间隔物导电。

公开(公告)号：WO1997032307A1

公开(公告)日：1997-09-04

申请号：PCT/US1997003305

申请日：1997-02-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  RYAN, Kevin, J.

IPC: G11C07/00

CPC classification number: G11C7/1072

Abstract: A synchronous memory device is described which is a relatively uncomplicated modification of an asynchronous DRAM such as a Burst Extended Data Out (BEDO) DRAM. The memory device receives the system clock signal, which provides many of those functions associated with the well known command signal CAS in asynchronous DRAMs. Chip and row select functions are controlled by the well known command signal RAS. Novel command signals CMND0 and CMND1 are supplied in place of the well known WE and OE command signals. The novel command signals are sampled at RAS time, at which time distinct combinations of the logic values of CMND0 and CMND1 represent distinct operating mode commands, such as Read, Write and Refresh. At each positive system clock edge following RAS time, the distinct combinations of the logic values of CMND0 and CMND1 represent distinct commands such as NOP, Switch Mode, and Latch Address. Full write command interrupt and/or byte-write capability can be provided, as desired.

Abstract translation: 描述了同步存储器件，其是诸如突发扩展数据输出（BEDO）DRAM的异步DRAM的相对简单的修改。 存储器装置接收系统时钟信号，其提供与异步DRAM中众所周知的命令信号CAS相关联的那些功能中的许多功能。 芯片和行选择功能由众所周知的命令信号RAS控制。 提供新的命令信号CMND0和CMND1来代替已知的WE和OE命令信号。 新的命令信号在RAS时间采样，此时CMND0和CMND1的逻辑值的不同组合表示不同的操作模式命令，如读，写和刷新。 在RAS时间之后的每个正系统时钟沿，CMND0和CMND1的逻辑值的不同组合表示不同的命令，如NOP，开关模式和锁存地址。 可以根据需要提供完全写入命令中断和/或字节写入功能。

公开(公告)号：WO1997030453A1

公开(公告)日：1997-08-21

申请号：PCT/US1997002652

申请日：1997-02-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  WRIGHT, Jeffrey, P. ,  ZHENG, Hua

IPC: G11C11/406

CPC classification number: G11C11/406

Abstract: A synchronous random access memory, such as a synchronous dynamic random access memory or a synchronous graphic random access memory, is responsive to command signals and includes multiple bank memory arrays. A command decoder/controller responds to command signals to initiate, in a first system clock cycle, an auto-refresh command controlling an auto refresh operation to a specified one of the multiple bank memory arrays.

Abstract translation: 诸如同步动态随机存取存储器或同步图形随机存取存储器的同步随机存取存储器响应命令信号并且包括多个存储体存储器阵列。 命令解码器/控制器响应于命令信号，以在第一系统时钟周期内启动控制对多个存储体存储器阵列中指定的一个的自动刷新操作的自动刷新命令。

公开(公告)号：WO1997024727A1

公开(公告)日：1997-07-10

申请号：PCT/US1996020784

申请日：1996-12-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  RYAN, Kevin, J. ,  WRIGHT, Jeffrey, P.

IPC: G11C07/00

CPC classification number: G11C7/1072 ,  G11C7/1039

Abstract: In a memory device such as a page-oriented synchronous dynamic random access memory device (SDRAM), a memory array and associated circuitry are divided into multiple internally defined circuit banks. Commands and addresses applied to the memory device affect all internal banks identically, but on a time-staggered basis. In an eight bank embodiment, activation of a selected row is first initiated in Bank0 by registration of an ACTIVE command and a coincident row address. One system clock cycle later, activation of the selected row is initiated in Bank1, and so on until activation of the selected row is initiated in Bank7 seven clock cycles after the intial registration of the command. A READ or WRITE command and coincident column address can be applied after the activation time limit has been met for the selected row in Bank0. The READ or WRITE command then affects successive banks in the above-described time staggered manner. Similarly, a PRECHARGE command can be applied when the read latency or write recovery time limit has been met for Bank0, and this command is executed in a time staggered manner in the successive banks. In a four bank embodiment, command registration and execution is staggered every two successive system clock cycles.

Abstract translation: 在诸如面向页面的同步动态随机存取存储器件（SDRAM）的存储器件中，存储器阵列和相关联的电路被分成多个内部限定的电路组。 应用于存储器设备的命令和地址对所有内部银行都是相同的，但是在时间上是交错的。 在八个银行实施例中，首先通过注册ACTIVE命令和一致的行地址来在Bank0中启动所选行的激活。 稍后一个系统时钟周期，在Bank1中启动所选行的激活，依此类推，直到在初始注册命令后七个时钟周期内在Bank7中启动所选行。 在Bank0中所选行的激活时间限制满足后，可以应用READ或WRITE命令和重合列地址。 READ或WRITE命令以上述时间交错的方式影响连续的存储体。 类似地，当Bank0的读延迟或写恢复时间限制已被满足时，可以应用PRECHARGE命令，并且该命令以连续存储体中的交错方式执行。 在四组实施例中，命令注册和执行每两个连续的系统时钟周期交错。

公开(公告)号：WO1997008700A1

公开(公告)日：1997-03-06

申请号：PCT/US1996013657

申请日：1996-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  KEETH, Brent

IPC: G11C07/00

CPC classification number: G11C7/18 ,  G11C7/065 ,  G11C11/4091

Abstract: A memory device has an array of memory cells which are positioned in a first block and a second block. The memory cells are arranged in rows and columns. A plurality of bit lines is coupled to the memory cells and a plurality of word lines is coupled to the memory cells. A sense amplifier is positioned between the first block and the second block, and a plurality of electrical connections is made between the sense amplifier and the bit lines. A plurality of isolation transistors is electrically connected in series with the electrical connections, the isolation transistors being located within the first and second blocks and spaced from the sense amplifier block.

Abstract translation: 存储器件具有位于第一块和第二块中的存储器单元阵列。 存储单元以行和列排列。 多个位线耦合到存储器单元，并且多个字线耦合到存储器单元。 感测放大器位于第一块和第二块之间，并且在感测放大器和位线之间形成多个电连接。 多个隔离晶体管与电连接串联电连接，隔离晶体管位于第一和第二块内并与读出放大器块间隔开。