ANTENNA SYSTEM FOR MOBILE OBJECT SATELLITE COMMUNICATION

    公开(公告)号:JPH0669714A

    公开(公告)日:1994-03-11

    申请号:JP22237492

    申请日:1992-08-21

    Applicant: NEC CORP

    Inventor: ICHIYOSHI OSAMU

    Abstract: PURPOSE:To provide an antenna for mobile satellite communication, in which an antenna for receiving a satellite radio wave in a horizontal direction by pure electronic type automatic control is tracked, a necessary antenna gain is easily obtained and a satellite can be acquired/ tracked in a vertical direction at an arbitrary elevation angle. CONSTITUTION:Plural antenna elements 1A-1H which are arranged radially in a circle from the center of a circle at equal angles and which can be adjusted in the vertical direction at a prescribed angle, coaxial cables 2A-2H which are connected to the antenna elements, switches 3A-3H which are connected to the other ends of the coaxial cables and which turn on/off high frequency signals and a switch control circuit which controls the plural switches so that the high frequency signals are simultaneously received at least to the antenna element becoming a center and to the antenna elements on the both sides of the antenna becoming the center are provided.

    FREQUENCY DIVIDER CIRCUIT
    102.
    发明专利

    公开(公告)号:JPH0590903A

    公开(公告)日:1993-04-09

    申请号:JP25075791

    申请日:1991-09-30

    Applicant: NEC CORP

    Inventor: ICHIYOSHI OSAMU

    Abstract: PURPOSE:To realize the circuit implementing phase frequency division correctly at all times without a phase jump caused in a conventional method. CONSTITUTION:The circuit is provided with a 1st limiter 1 receiving a complex signal sample string comprising a real part and an imaginary part and setting the amplitude of the complex signal string to a unit value, a 1st complex multiplier 2 implementing the complex multiplication between an output signal of the 1st limiter and a complex conjugate value A inputted from an attached terminal A, and a 2nd complex multiplier 3 receiving an output signal of the 1st complex multiplier and applying complex number multiplication between the signal and a complex conjugate value B inputted from an attached terminal B, and an output signal of the 2nd complex multiplier becomes a complex conjugate value B generated via a 2nd limiter 4 and a one sample delay device 5 and is fed back to the attached terminal B and fed back to the attached terminal A as the complex conjugate value A generated via an N-multiplier circuit 6 receiving the output signal of the 2nd limiter and implementing the multiplication of power N.

    FREQUENCY DIVISION MULTIPLEX SIGNAL DEMULTIPLEXER CIRCUIT

    公开(公告)号:JPH04117739A

    公开(公告)日:1992-04-17

    申请号:JP23879990

    申请日:1990-09-06

    Applicant: NEC CORP

    Inventor: ICHIYOSHI OSAMU

    Abstract: PURPOSE:To realize a public line network having a transmission line for a broad band signal by providing a means able to reduce a sampling period in a serial/parallel conversion circuit to the demultiplexer circuit. CONSTITUTION:The demultiplexer circuit is provided with N-sets of delay devices 2 providing a prescribed time delay to each of signals outputted from a serial/parallel conversion circuit 1 and with N-sets of sub filters 3 receiving the signal and applying filtering to the signal in the unit of N samples, and also with a high speed Fourier transformation circuit 4 which selects and filters a k-th signal among N sets of parallel signals at a frequency location being the center frequency among the frequencies in the received signal series, transfers the frequency to zero thereby obtaining a base band signal. Moreover, the demultiplexer is provided with a matrix switch 5 which receives signals outputted from the N-sets of the sub filters 3 and outputs N-sets of signals, and outputs a (1-i(mod N))-th input signal to the high speed Fourier transformation circuit 4 as a 1st (i=0, 1, 2,..., N-1) output of its own switch at a time equivalent to an i-th (i=n-mN, m is an integer) among divisions of the reception signal string by each of N samples. Thus, a public line network having a transmission line is realized.

    FREQUENCY DIVISION MULTIPLEXER
    104.
    发明专利

    公开(公告)号:JPH04117738A

    公开(公告)日:1992-04-17

    申请号:JP23879890

    申请日:1990-09-06

    Applicant: NEC CORP

    Inventor: ICHIYOSHI OSAMU

    Abstract: PURPOSE:To send a signal having a broad band frequency spectrum by using a matrix switch to select an output of a high speed inverse Fourier transformation means and giving the selected output to a sub filter. CONSTITUTION:The multiplexer is provided with a high speed inverse Fourier transformation means 1 receiving N-sets of input signal series, N-sets of sub filters 2 applying filtering to the signal in the unit of N samples, a delay circuit network 3 delaying each output of the sub filters 2 by a prescribed sample number and an adder circuit 4 calculating total sum of outputs of the delay circuit network 3 to generate a frequency division multiplex signal. Moreover, the multiplexer is provided with a matrix switch 5 receiving an output of the high speed inverse Fourier transformation means 1 and outputting N-sets of signals and the 1st sub filter 2 corresponds to a (1+1)th output the matrix switch 5 with respect to modulus N when an input signal of the high speed inverse Fourier transformation means 1 relates to an i-th timing among divisions of the sampling timing by N. Thus, high speed data transmission is implemented and a wide band signal is sent.

    SIGNAL MULTIPLEX CIRCUIT AND SIGNAL DEMULTIPLEX CIRCUIT

    公开(公告)号:JPH0444432A

    公开(公告)日:1992-02-14

    申请号:JP15156490

    申请日:1990-06-12

    Applicant: NEC CORP

    Inventor: ICHIYOSHI OSAMU

    Abstract: PURPOSE:To realize a channel of an optional band width as required by delaying 0th to (N-1)th filtered signals by delay of 0-(N-1) samples respectively, adding the results, converting the sum into a serial signal and outputting the serial signal as a signal subject to FDM multiplexing. CONSTITUTION:The circuit is provided with 1st-(N-l)th frequency conversion circuits 4-1-4-(N-1) and a k-th frequency conversion circuit 4-k applies frequency conversion of 0(Hz) fk=k.DELTAf(Hz). The center frequency of an input signal is frequency-converted from 0(Hz) to fk(Hz). Then the signal is given to filters 2-0-2-(N-1) tuned to a same frequency fk. Thus, a filter bank having a completely flat frequency characteristic in a band of each channel is realized.

    ANTENNA CONTROL CIRCUIT
    106.
    发明专利

    公开(公告)号:JPH03267783A

    公开(公告)日:1991-11-28

    申请号:JP6657690

    申请日:1990-03-16

    Abstract: PURPOSE:To surely control the direction of an antenna at a high speed even when the band width of an AGC loop is narrow by calculating the means value and variance value of received IF signal levels and comparing them with values which are set previously. CONSTITUTION:A signal from a communication satellite, etc., which is received through a tracking type directional antenna 1 is converted by a converter 2 into an IF signal and an AGC amplifier 3 attracts and outputs long-time means level variation. Then a direction controller 12 generates an antenna tracking signal with the mean value of the output signal of a level detector 4, so variation in the level of the output can accurately be detected. The output signal, however, is controlled so that the long-time mean level variation is made nearly constant regardless of the direction of the antenna 1, so the arithmetic result from the mean value and variance value of the output signal of the detector 4 is compared with the preset values to judge whether or not the direction of the antenna 1 is proper. Consequently, the best reception direction of the antenna 1 can surely be determined at a high speed.

    DEMODULATION CIRCUIT
    107.
    发明专利

    公开(公告)号:JPH03245641A

    公开(公告)日:1991-11-01

    申请号:JP4312490

    申请日:1990-02-23

    Applicant: NEC CORP

    Inventor: ICHIYOSHI OSAMU

    Abstract: PURPOSE:To attain synchronization locking surely and quickly by employing a transmultiplexer type synthesis means receiving a signal from a switch means and using a filter bank whose frequency interval is f and whose respective band width is wider than f so as to apply frequency division multiplex. CONSTITUTION:An N-set of band pass filters whose band width is wider than f are arranged in a filter bank TDUX 9 at a frequency interval of f. A base band switch circuit 11 receives other complex signal groups in two- branched complex signal groups outputted from N-set of band pass filters of the TDUX 9 and selects a band pass filter represented by a selection signal Sc outputted from a carrier detection circuit 10 to pass through only a relevant signal in other signal group. A MUX 12 receives a complex signal outputted from the base band switch circuit 11 and applies frequency division multiplex with the filter bank whose band width is wider than f and whose frequency interval is f.

    PHASE SYNCHRONIZING CIRCUIT
    108.
    发明专利

    公开(公告)号:JPH02170621A

    公开(公告)日:1990-07-02

    申请号:JP32420588

    申请日:1988-12-22

    Applicant: NEC CORP

    Inventor: ICHIYOSHI OSAMU

    Abstract: PURPOSE:To expand range of the acquisition of synchronizm by prefixing N bits in the same logical condition at the code bit of a digital signal at K bits, adding '+1' when a phase changes from a second quadrant to a third quadrant, and adding '-1' in an opposite case. CONSTITUTION:A converting ROM 7 outputs a digital signal at K=eight bits indicating phase information to a quadrant detector 8 and a same value bit adding circuit 14. A quadrant change detector 10 subtracts the output quadrant signal of a delay device 9 from the output quadrant signal of the quadrant detector 8. When the phase changes from a second quadrant to a third quadrant, the digital signal at N=four bits having the contents of '+1' is outputted, when the phase changes from the third quadrant to the second quadrant, the digital signal at four bits having the contents of '-1' is outputted, and in the other cases, the digital signal at four bits having the contents of '0' is outputted. Thus, since the chase comparing characteristic is not periodical, and it is proportional to the phase change, the range of the acquisition of synchronizm can be expanded.

    SATELLITE COMMUNICATION/POSITION MEASURING SYSTEM FOR MOVING BODY

    公开(公告)号:JPH021583A

    公开(公告)日:1990-01-05

    申请号:JP14311288

    申请日:1988-06-10

    Applicant: NEC CORP

    Inventor: ICHIYOSHI OSAMU

    Abstract: PURPOSE:To constitute the title system so that communication and a position measurement can be executed in all areas on the earth by transmitting a position measuring signal so as to reach simultaneously plural communication satellites, executing the position measurement with regard to each of receiving position measuring signals of a prescribed frequency portion, and as a result, adopting a coincidence value as a position measured value. CONSTITUTION:The delay quantity outputted to timing controllers 9-1 - 9-3 from time difference detecting devices 8-1 - 8-3, and the one-way propagation time extending from a base station to communication satellites 2-1 - 2-3 are denoted as Ci (i=1-3) and Ti (i=1-3), respectively. As a result, measured values Di (i=1-3) by the time difference detecting devices 8-1 - 8-3 become Di=Ci+2Ti. Therefore, in the case of T0=Ci+ Ti and Ci=2T0-Di, three position measuring signals transmitted from the base station reach each communication satellite simultaneously, that is, after T0 second from the time when they have been generated by a signal generator 10, and radiated simultaneously from each communication satellite. Accordingly, a moving body 11 detects an arrival time difference of the position measuring signals arriving from each communication satellite and can measure its own geographical position by using a method of a trigonometrical position measurement.

    CHIRP FILTER
    110.
    发明专利

    公开(公告)号:JPH01311715A

    公开(公告)日:1989-12-15

    申请号:JP14311188

    申请日:1988-06-10

    Applicant: NEC CORP

    Inventor: ICHIYOSHI OSAMU

    Abstract: PURPOSE:To realize an accurate chirp rate by arranging a transmultiplexer type filter bank to a pre-stage and a post stage of a delay device group operated as a spread delay circuit of a chirp filter. CONSTITUTION:Filters having the same frequency characteristic are arranged to a transmultiplexer type filter bank branching circuit 2 so that the frequency bands are overlapped with each other, a filter band having a continuous fre quency characteristic entirely applies filter processing to plural base band signal inputs and the result is outputted to a corresponding delay device group 3 from a port of number (k). The delay device group 3 applies a delay of (k+[N/2]-1). tau as to the output at the port (k). Then the transmultiplexer type filter bank branching circuit 4 receives a corresponding output from the delay device group 3 respectively and gives a signal output to a frequency location corresponding to the port (k) to synthesize the outputs. Thus, the chirp rate is given as tau/ f and the values tau, f are set to optional values accu rately.

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