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公开(公告)号：DE69729681D1
公开(公告)日：2004-08-05
申请号：DE69729681
申请日：1997-04-14
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: A variable-bandwidth frequency-division multiplex communication system which needs no interpolation circuits, but uses switch element of simple structure. The system includes a signal combining circuit which has N A/D converters associated respectively with independent information signals to be transmitted, a complex local oscillator for generating complex signals each having a frequency k DELTA f (1 ≤ k≤ N-1), DELTA f being the channel frequency interval, N complex multipliers for multiplying the outputs of the A/D converters by the respective complex signals, and producing N output signals, a circuit for effecting an inverse Fourier transform of N points, an N x N switch circuit connected between the outputs of the complex multipliers and input terminals of the inverse Fourier transform circuit, N digital subfilters connected respectively to the outputs of the inverse Fourier transform circuit, N delay units connected respectively to outputs of the digital subfilters, and an adder for adding output signals from the delay units and outputting a sum signal.
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公开(公告)号：CA2052589C
公开(公告)日：1997-12-23
申请号：CA2052589
申请日：1991-10-04
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: A first clock signal of f1 in frequency is converted into a second clock signal having a frequency of f2 = ~ f1. The first clock signal is converted by a tank circuit (12) and a converter (13) into an R-bit first phase signal (~1) indicating the phase of the first clock signal. The first phase signal is multiplied by n (mod 2R) by a multiplier into a second phase signal (~3). The second phase signal is supplied to a digital phase-locked loop (PIL) (3) consisting of a subtractor (15), a low-pass filter (LPF) (16), a numerically controlled oscillator (NCO) (17) and a multiplier (18). The multiplier in the digital PIL (3) multiplies by m (mod 2R) a third phase signal, indicating the phase of a second clock signal which is the output of the NCO (17), to generate a fourth phase signal. The subtractor (15) generates a signal representing the phase error between the second and fourth phase signals. This phase error signal is filtered by the LPF (16) to control the oscillating phase of the NCO (17). A clock generating circuit generates, on the basis of the third phase signal, the second clock signal.
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公开(公告)号：DE69124904D1
公开(公告)日：1997-04-10
申请号：DE69124904
申请日：1991-10-04
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: A first clock signal of f1 in frequency is converted into a second clock signal having a frequency of f2 = n/m f1. The first clock signal is converted by a tank circuit (12) and a converter (13) into an R-bit first phase signal ( theta 1) indicating the phase of the first clock signal. The first phase signal is multiplied by n (mod 2 ) by a multiplier into a second phase signal ( theta 3). The second phase signal is supplied to a digital phase-locked loop (PIL) (3) consisting of a subtractor (15), a low-pass filter (LPF) (16), a numerically controlled oscillator (NCO) (17) and a multiplier (18). The multiplier in the digital PIL (3) multiplies by m (mod 2 ) a third phase signal, indicating the phase of a second clock signal which is the output of the NCO (17), to generate a fourth phase signal. The subtractor (15) generates a signal representing the phase error between the second and fourth phase signals. This phase error signal is filtered by the LPF (16) to control the oscillating phase of the NCO (17). A clock generating circuit generates, on the basic of the third phase, signal, the second clock signal.
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公开(公告)号：CA2079422C
公开(公告)日：1996-07-02
申请号：CA2079422
申请日：1992-09-29
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: In a phase-locked circuit which is operable in response to an input complex signal to produce an output complex signal, a first complex multiplication is carried out between the input and the output complex signals to obtain a phase difference therebetween which appears as a complex phase difference. The complex phase difference is composed of a real part and an imaginary part which are individually allowed to pass through a low pass filter and to be supplied to a numerically controlled oscillator as a control signal. The control signal includes a frequency component even when the phase-locked circuit is put into an asynchronous state. The low pass filter may be replaced by a digital circuit comprising phase dividers.
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公开(公告)号：DE3855244D1
公开(公告)日：1996-06-05
申请号：DE3855244
申请日：1988-02-16
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: An N-channel FDM signal is converted into complex signals of baseband frequencies (1-6) spaced at intervals equal to frequency DELTA f. The complex baseband signals are converted first into digital samples (7-9)having a frequency N DELTA f and then into N parallel digital signals (11). A plurality of first FIR subfilters (17-1 through 17-N) respectively perform filtering on each of the parallel digital signals at frequency DELTA f to produce a first series of filtered digital signals from each of the first FIR subfilters, and (m - 1) groups of second FIR subfilters respectively perform filtering on each of the parallel digital signals at frequency DELTA f to produce a second series of filtered digital samples from each of the second FIR subfilters at timing displaced with respect to the first series by a/m DELTA f, where is an integer ranging from unity to (m - 1) and m is an integer equal to or greater than 2. Outputs of the first FIR subfilters are combined with outputs of the second FIR subfilters to produce N summation outputs at frequency m DELTA f. An N-point Fast Fourier Transform processor (14) performs fast Fourier transform on the N summation outputs at frequency m DELTA f to derive digital channels. Because of the oversampling at frequency m DELTA f, each of the digital channels has a frequency response which can be made flat over the bandwidth DELTA f.
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Patent Agency Ranking
公开(公告)号：AU656100B2
公开(公告)日：1995-01-19
申请号：AU2531392
申请日：1992-09-22
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04L27/227 , H04L27/00 , H04L27/22 , H04L27/233 , H03D3/00
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公开(公告)号：AU8678091A
公开(公告)日：1992-04-30
申请号：AU8678091
申请日：1991-10-25
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04L27/227 , H03L7/099 , H04L7/00 , H04L7/02 , H04L7/027 , H04L7/033 , H04L27/00 , H04L27/22 , H04L27/233 , H03D3/06
Abstract: A digital output of a quasi-coherent detection circuit (2) is M-th power multiplied and then processed by a set of digital filters to generate signals for coherent detection and clock interpolation. The digital output of the quasi-coherent detection circuit (2) is also fed, through a delay circuit (19), to coherent detection circuit which in turn processes the digital output of the quasi-coherent detection circuit, using the coherent detection signal. Timing error information indicative of the difference between phases of an interpolated clock and the interpolation signal determines the weighting factor of data interpolation channel filter (18) which in turn interpolate and output coherent-detected data signal.
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公开(公告)号：CA2054247A1
公开(公告)日：1992-04-26
申请号：CA2054247
申请日：1991-10-25
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04L27/227 , H03L7/099 , H04L7/00 , H04L7/02 , H04L7/027 , H04L7/033 , H04L27/00 , H04L27/22 , H04L27/233
Abstract: A digital output of a quasi-coherent detection circuit (2) is M-th power multiplied and then processed by a set of digital filters to generate signals for coherent detection and clock interpolation. The digital output of the quasi-coherent detection circuit (2) is also fed, through a delay circuit (19), to coherent detection circuit which in turn processes the digital output of the quasi-coherent detection circuit, using the coherent detection signal. Timing error information indicative of the difference between phases of an interpolated clock and the interpolation signal determines the weighting factor of data interpolation channel filter (18) which in turn interpolate and output coherent-detected data signal.
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公开(公告)号：DE69132309T2
公开(公告)日：2000-12-14
申请号：DE69132309
申请日：1991-10-25
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04L27/227 , H03L7/099 , H04L7/00 , H04L7/02 , H04L7/027 , H04L7/033 , H04L27/00 , H04L27/22 , H04L27/233
Abstract: A digital output of a quasi-coherent detection circuit (2) is M-th power multiplied and then processed by a set of digital filters to generate signals for coherent detection and clock interpolation. The digital output of the quasi-coherent detection circuit (2) is also fed, through a delay circuit (19), to coherent detection circuit which in turn processes the digital output of the quasi-coherent detection circuit, using the coherent detection signal. Timing error information indicative of the difference between phases of an interpolated clock and the interpolation signal determines the weighting factor of data interpolation channel filter (18) which in turn interpolate and output coherent-detected data signal.
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