-
公开(公告)号：JP2002040994A
公开(公告)日：2002-02-08
申请号：JP2000222577
申请日：2000-07-24
Applicant: SEIKO EPSON CORP
Inventor： OZAWA NORIO , ISHIGURO HIDETO , MATSUEDA YOJIRO
Abstract: PROBLEM TO BE SOLVED: To obtain high-quality display by suppressing unevenness of display. SOLUTION: In this optoelectronic device, sub-pixels 120a, 120b, 120c are provided corresponding to intersections of 3m lines of scanning line 112 which are elongated and formed by being made to exist in an X direction and pair lines of (n) lines of digital data lines 114 and analog data lines which are elongated and formed by being made to exist in a Y direction and sub-pixels adjacent with each other in the Y direction are driven collectively as one pixel. In this case, in the first mode, respective sub-pixels constituting one pixel are turned ON or OFF in accordance with gradation data indicating the gradation of the pixel and, on the other hand, in the second mode, a voltage signal indicating the gradation of the pixel is applied in common to the sub-pixels constituting one pixel. Moreover, in the first case in the second mode, a voltage signal is supplied to analog data lines in a line sequential manner by a first data line driving circuit 180 and, on the other hand, in the second case, a voltage signal is supplied to the analog data lines in a point sequential manner by a second data line driving circuit 190.
-
公开(公告)号：JP2000357584A
公开(公告)日：2000-12-26
申请号：JP16755699
申请日：1999-06-14
Applicant: SEIKO EPSON CORP
Inventor： KIMURA MUTSUMI , MAEDA HIROSHI , MATSUEDA YOJIRO , KITAWADA KIYOBUMI
Abstract: PROBLEM TO BE SOLVED: To provide a circuit board for a luminescent element capable of preventing voltage drop in a common electrode so as to achieve bright image displaying. SOLUTION: A circuit board for a luminescent element is suitable for forming an electroluminescent element for emitting light with application of a current. In particular, the circuit board comprises: a loading-out terminal group 6 having loading-out terminals 61 to the outside integrated on one side of the board; and a contact pattern 2 interposed between a common electrode 10 for allowing a common current to flow therein and the loading-out terminal group 6, for electrically connecting the common electrode 10 to some of the loading-out terminals 61 in the loading-out terminal group 6.
-
公开(公告)号：JP2000356963A
公开(公告)日：2000-12-26
申请号：JP16755599
申请日：1999-06-14
Applicant: SEIKO EPSON CORP
Inventor： KIMURA MUTSUMI , MAEDA HIROSHI , MATSUEDA YOJIRO , KITAWADA KIYOBUMI
IPC: G09F9/30 , H01L21/336 , H01L29/786 , H01L51/50 , H05B33/08 , H05K1/11
Abstract: PROBLEM TO BE SOLVED: To provide the arrangement and manufacturing method of the circuit of a display device in which unevenness of interpixel luminance and of the entire of a screen is not generated. SOLUTION: A thin film transistor 12 is provided between a power supply line 203 constituting the power source of an electroluminescent layer and a pixel electrode 205 for supplying current to the electroluminescent layer. The gate electrode 202 of the thin film transistor 12 is formed longitudinally. In addition, a first contact hole 303 for being connected to the pixel electrode 205 is formed longitudinally, and a second contact hole 304 for being connected to the power supply line 203 is formed longitudinally. The gate electrode 202 and the contact holes 303, 304 are disposed parallel with each other in the longitudinal direction and orthogonal to the carrier flow direction. As the result, it is possible to supply current to the electroluminescent element 10 uniformly in the shortest distance without leader wiring.
-
公开(公告)号：JP2000193939A
公开(公告)日：2000-07-14
申请号：JP2000035189
申请日：2000-02-14
Applicant: SEIKO EPSON CORP
Inventor： MATSUEDA YOJIRO
Abstract: PROBLEM TO BE SOLVED: To eliminate the flicker and the burn-in and after-image and to make a liquid crystal to be hardly degraded by making the range of the potential difference between the potential of a picture input signal of a first field and the potential of a scanning signal so as to overlap with the range of the potential difference of that with a second field to suppress an effect due to a shifted voltage to the minimum. SOLUTION: The polarity of the potential 1 of a signal line is inverted for every field, but even when the polarity of the signal line is a positive polarity or a negative polarity, potentials of all the signals are within the voltage range between V1 and V2. The potential 4 of a counter electrode is set for every field to VC1 and VC2 and it is inverted with a phase opposite to the polarity inversion of the signal line. The potential 2 of a scanning line becomes a selection level VH only in the period of T1 and becomes a non-selection level VL in the period of T2. The potential 3 of a pixel electrode becomes equal to the potential 1 of the signal line in the period of T1 because an active element is brought into conduction and is shifted to a low voltage side by a voltage equivalent to ΔV+ at the same time when the potential 2 of the scanning line is changed from VH to VL. Then, a liquid crystal is driven by impressing the positive signal and the negative signal on the pixel electrode alternately for every field.
-
公开(公告)号：JP2000147463A
公开(公告)日：2000-05-26
申请号：JP37118099
申请日：1999-12-27
Applicant: SEIKO EPSON CORP
Inventor： MATSUEDA YOJIRO
Abstract: PROBLEM TO BE SOLVED: To obtain a uniform and highly fine picture quality in which deviations of dots and color slippages or the like are not generated on a screen by arranging respective terminals of clock lines, video lines and power lines at the side of one side of a display device to prevent deviations from being generated in timings when video signals are written on signal lines. SOLUTION: Respective terminals of clock lines 12 to 15, power lines 16, 17 and video lines 18 to 20 are arranged so as to exist at the side of one side of the device. Consequently, deviations are not generated in timings when video signals V1 to V3 are written on signal lines X1, X2, X3, X4,.... Then, the power lines 16 and 17 are arranged between the clock lines 12 to 15 and the video lines 18 to 20. Moreover, supplies of these power lines 16, 17 are performed from the same B direction as a first noise conter-measure. Furthermore, clock lines 12 and 13, 15 and 16 are made to be crossed each other respectively as a second noise countermeasure.
-
Patent Agency Ranking106.发明专利
公开(公告)号：JPH11330483A
公开(公告)日：1999-11-30
申请号：JP13890598
申请日：1998-05-20
Applicant: SEIKO EPSON CORP
Inventor： MATSUEDA YOJIRO
IPC: G02F1/136 , G02F1/1368 , H01L21/336 , H01L29/786
Abstract: PROBLEM TO BE SOLVED: To electrically conduct respective semiconductor layers subjected to different ion implantation in the same wiring layer well while enhancing a numerical aperture as an electrooptic device. SOLUTION: In an ion implanting process for forming two semiconductor layers, i.e., a drain region 12 and a contact part 16, in the same wiring layer when a TFT 21 is fabricated in a liquid crystal having a plurality of wiring layers by connecting two semiconductor layers electrically, both ions are implanted while being overlapped into the boundary of the drain region 12 and the contact part 16 and they are connected by making a contact hole C2 in a region including the boundary region, the drain region 12 and the contact part 16.
-
公开(公告)号：JPH11311809A
公开(公告)日：1999-11-09
申请号：JP6850799
申请日：1999-03-15
Applicant: SEIKO EPSON CORP
Inventor： MATSUEDA YOJIRO
IPC: H01L29/786 , G02F1/1345 , G02F1/136 , G02F1/1365 , G02F1/1368 , H01L21/336
Abstract: PROBLEM TO BE SOLVED: To prolong the life without deteriorating the liquid crystal by preventing a DC voltage from being applied to the liquid crystal by providing divided peripheral electrodes at the periphery of pixel electrodes. SOLUTION: The liquid crystal is sandwiched between a couple of substrates, one of which has TFTs 1 connected to the scanning lines Y, and signal lines X, and pixel electrodes 2 which are connected to the TFTs 1 and arranged in matrix. Then divided peripheral electrodes 13a to 13c are arranged at the periphery of the pixel electrodes 2 which are arranged in matrix. The peripheral electrodes 13a to 13c are held preferably at the same potential with a counter electrode. Thus, the peripheral electrodes 13a to 13c are provided to cut off an electric field between the scanning lines Y and signal lines X, and counter electrode, thereby preventing the DC voltage from being applied to the liquid crystal. Similarly, even a device using thin-film nonlinear elements instead of the TFTs 1 only needs to be equipped with peripheral electrodes in a peripheral area adjacent to pixel electrodes on a 1st insulating substrate. In this case, the potential of the peripheral electrodes is preferably equal to the potential of the signal electrodes.
-
公开(公告)号：JPH08227283A
公开(公告)日：1996-09-03
申请号：JP3271295
申请日：1995-02-21
Applicant: SEIKO EPSON CORP
Inventor： MATSUEDA YOJIRO
IPC: G02F1/136 , G02F1/133 , G02F1/1368 , G09G3/20 , G09G3/36
Abstract: PURPOSE: To provide an image display matching with an optional gradation display charactristic by providing a data conversion circuit converting the digital input video data of n bits to n+m bits and a digital data driver of n+m bits. CONSTITUTION: The digital image signal data 16 of (n) bits are converted to the digital image signal data of n+m bits by a data conversion circuit. At this time, a γ characteristic correcting ROM 15 is used as the data conversion circuit. That is, a γcharacteristic of a liquid crystal is measured really, and when the address of the ROM is made the data of (n) bits of an input image signal, and the output is made the data of n+m bits converting to the required γcharacteristic beforehand, the data are converted successively simply. Thus, the digital input signal of n bits is converted successively to the digital data of n+m bits matching with the γ characteristic of the liquid crystal by the ROM 15, and the gradation display by (n) bits is performed by using a digital data driver 2 of n+m bits.
-
公开(公告)号：JPH06250606A
公开(公告)日：1994-09-09
申请号：JP3178293
申请日：1993-02-22
Applicant: SEIKO EPSON CORP
Inventor： MATSUEDA YOJIRO
Abstract: PURPOSE:To set a power source voltage to be an optimal value and to suppress the malfunction of the shift register of a driver and the generation of a noise while keeping the writing and holding characteristics in a TFT type liquid crystal display device. CONSTITUTION:The positive power source voltage Vddy and the negative power source voltage Vssy of a scanning line driving circuit are set as the following equation: Vddy>=Vidd2+DELTAVy2, where, Vid2: the maximum value of a picture signal, DELTAVy2: a voltage between a gate and a source in which the ON resistance Ron of an N-type pixel TFT satisfies the following equation specifying a writing ratio larger than k%: Vssy
-
公开(公告)号：JPH05333316A
公开(公告)日：1993-12-17
申请号：JP14031892
申请日：1992-06-01
Applicant: SEIKO EPSON CORP
Inventor： MATSUEDA YOJIRO
Abstract: PURPOSE:To realize a uniform picture having no high contrast and no crosstalk by optimizing the structure, picture element circuit and driving method of a TFT and impressing a driving voltage sufficient for liquid crystal. CONSTITUTION:A TFT 3 is arranged at the intersection of a signal line 1 and a scanning line 2 which are arranged in a grid-shape and the TFT 3 is used as a switch and writes image signals in a liquid crystal capacitor and holding capacitor 6. At the TFT 3, resistor parts 4 are provided between a drain electrode D and the signal line 1 and between a source electrode S and a picture element electrode, and the pressure resistance of the TFT 3 is improved by decreasing this resistance value so as to decrease a leak current. Namely, two inequalities are established among a resistance value RT between the source and drain of the TFT 3 in the ON state, resistance value RL of the resistor parts 4, resistance value RO of a liquid crystal layer, capacity value C0, holding capacity Cs, one horizontal period TH and one vertical period T.
-
-
-
-
-
-
-
-
-
Search Results
202
records
(took 0.03 seconds)
