公开(公告)号：US10069034B2

公开(公告)日：2018-09-04

申请号：US15588896

申请日：2017-05-08

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Jinwei Yang ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/00 ,  H01L33/14 ,  H01L33/04 ,  H01L31/0224 ,  H01L31/0352 ,  H01L31/105 ,  H01L33/32

CPC classification number: H01L33/002 ,  H01L31/022408 ,  H01L31/035236 ,  H01L31/105 ,  H01L33/0062 ,  H01L33/025 ,  H01L33/04 ,  H01L33/145 ,  H01L33/32 ,  H01L2933/0008

Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.

公开(公告)号：US20180122987A1

公开(公告)日：2018-05-03

申请号：US15856920

申请日：2017-12-28

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Jinwei Yang ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/12 ,  H01L33/46 ,  H01L33/06 ,  G06F17/50 ,  H01L33/00 ,  H01L33/32 ,  C30B29/40 ,  H01L33/14 ,  H01L33/40

CPC classification number: H01L33/12 ,  C30B29/403 ,  G06F17/505 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/145 ,  H01L33/32 ,  H01L33/405 ,  H01L33/46

Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.

公开(公告)号：US20180108805A1

公开(公告)日：2018-04-19

申请号：US15856596

申请日：2017-12-28

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Remigijus Gaska ,  Jinwei Yang ,  Michael Shur ,  Alexander Dobrinsky

IPC: H01L33/06 ,  H01L33/32 ,  H01L33/00 ,  H01L29/15 ,  H01L29/20 ,  B82Y10/00 ,  H01L29/207 ,  H01L29/201 ,  B82Y20/00 ,  H01L33/04 ,  H01S5/20 ,  H01S5/32 ,  H01S5/343 ,  H01S5/34

CPC classification number: H01L33/06 ,  B82Y10/00 ,  B82Y20/00 ,  H01L29/15 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/207 ,  H01L33/0075 ,  H01L33/04 ,  H01L33/32 ,  H01S5/2009 ,  H01S5/3211 ,  H01S5/3216 ,  H01S5/3407 ,  H01S5/34333

Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).

公开(公告)号：US20170256672A1

公开(公告)日：2017-09-07

申请号：US15602677

申请日：2017-05-23

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Jinwei Yang ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/00 ,  H01L33/32 ,  H01L33/06

CPC classification number: H01L33/0025 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/04 ,  H01L33/06 ,  H01L33/12 ,  H01L33/145 ,  H01L33/32

Abstract: Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.

公开(公告)号：US20170186910A1

公开(公告)日：2017-06-29

申请号：US15457088

申请日：2017-03-13

Applicant: Sensor Electronic Technology, Inc.

Inventor： Michael Shur ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Remigijus Gaska ,  Jinwei Yang

IPC: H01L33/06 ,  H01L33/22 ,  H01S5/343 ,  H01L33/40 ,  H01S5/125 ,  H01S5/30 ,  H01L33/32 ,  H01L33/00

CPC classification number: H01L33/06 ,  B82Y10/00 ,  B82Y20/00 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/15 ,  H01L29/2003 ,  H01L29/778 ,  H01L33/0025 ,  H01L33/10 ,  H01L33/22 ,  H01L33/32 ,  H01L33/325 ,  H01L33/405 ,  H01S5/125 ,  H01S5/3054 ,  H01S5/3063 ,  H01S5/343 ,  H01S5/34333 ,  H01S5/34346

Abstract: A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.

公开(公告)号：US09660133B2

公开(公告)日：2017-05-23

申请号：US14493388

申请日：2014-09-23

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Jinwei Yang ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/00 ,  H01L33/06 ,  H01L33/12 ,  H01L33/04 ,  H01L33/32 ,  H01L33/14

CPC classification number: H01L33/0025 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/04 ,  H01L33/06 ,  H01L33/12 ,  H01L33/145 ,  H01L33/32

Abstract: Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.

公开(公告)号：US09634183B2

公开(公告)日：2017-04-25

申请号：US15069272

申请日：2016-03-14

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Remigijus Gaska ,  Jinwei Yang ,  Michael Shur ,  Alexander Dobrinsky

IPC: H01L33/06 ,  H01L33/32 ,  H01L33/00 ,  B82Y10/00 ,  B82Y20/00 ,  H01L29/20 ,  H01L29/15 ,  H01L33/04 ,  H01L29/201 ,  H01S5/20 ,  H01S5/32 ,  H01S5/34 ,  H01S5/343 ,  H01L29/207

CPC classification number: H01L33/06 ,  B82Y10/00 ,  B82Y20/00 ,  H01L29/15 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/207 ,  H01L33/0075 ,  H01L33/04 ,  H01L33/145 ,  H01L33/32 ,  H01L33/325 ,  H01S5/2009 ,  H01S5/3211 ,  H01S5/3216 ,  H01S5/3407 ,  H01S5/34333

Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).

公开(公告)号：US09543400B2

公开(公告)日：2017-01-10

申请号：US14973563

申请日：2015-12-17

Applicant: Sensor Electronic Technology, Inc.

Inventor： Remigijus Gaska ,  Michael Shur ,  Jinwei Yang ,  Alexander Dobrinsky ,  Maxim S. Shatalov

IPC: H01L31/072 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778 ,  H01L21/285 ,  H01L29/40 ,  H01L33/00 ,  H01L29/15 ,  H01L29/20 ,  H01L29/205 ,  H01L33/14 ,  H01L29/737 ,  H01L33/06 ,  H01L33/32 ,  H01L29/201 ,  H01L33/40

CPC classification number: H01L29/452 ,  H01L21/28575 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/401 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/737 ,  H01L29/778 ,  H01L29/7786 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/14 ,  H01L33/32 ,  H01L33/40 ,  H01L33/405 ,  H01L2933/0016

Abstract: A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the semiconductor layer. Subsequently, one or more layers of a device heterostructure are formed on the non-masked region(s) of the semiconductor layer. The ohmic contact can be formed after the one or more layers of the device heterostructure are formed. The ohmic contact formation can be performed at a processing temperature lower than a temperature range within which a quality of a material forming any semiconductor layer in the device heterostructure is damaged.

Abstract translation: 提供了用于形成与半导体层的欧姆接触的解决方案。 掩模材料被施加到半导体层表面上的一组接触区域。 随后，在半导体层的非掩蔽区域上形成一层或多层器件异质结构。 欧姆接触可以在形成器件异质结构的一个或多个层之后形成。 欧姆接触形成可以在低于在器件异质结构中形成任何半导体层的材料的质量被损坏的温度范围的处理温度下进行。

公开(公告)号：US20160315219A1

公开(公告)日：2016-10-27

申请号：US15200313

申请日：2016-07-01

Applicant: Sensor Electronic Technology, Inc.

Inventor： Michael Shur ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Remigijus Gaska ,  Jinwei Yang

IPC: H01L33/06 ,  H01L33/32 ,  H01S5/30 ,  H01S5/343 ,  H01L33/10 ,  H01S5/125 ,  H01L33/00 ,  H01L33/22

CPC classification number: H01L33/06 ,  B82Y10/00 ,  B82Y20/00 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/15 ,  H01L29/2003 ,  H01L29/778 ,  H01L33/0025 ,  H01L33/10 ,  H01L33/22 ,  H01L33/32 ,  H01L33/325 ,  H01L33/405 ,  H01S5/125 ,  H01S5/3054 ,  H01S5/3063 ,  H01S5/343 ,  H01S5/34333 ,  H01S5/34346

Abstract: A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.

公开(公告)号：US09412901B2

公开(公告)日：2016-08-09

申请号：US14675596

申请日：2015-03-31

Applicant: Sensor Electronic Technology, Inc.

Inventor： Michael Shur ,  Remigijus Gaska ,  Jinwei Yang ,  Alexander Dobrinsky

IPC: H01L33/06 ,  H01L33/18 ,  H01L33/00 ,  H01L33/32

CPC classification number: H01L33/06 ,  H01L33/0045 ,  H01L33/18 ,  H01L33/32

Abstract: A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another. Furthermore, the superlattice layer can be configured to be at least partially transparent to radiation, such as ultraviolet radiation.