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公开(公告)号：US10297460B2
公开(公告)日：2019-05-21
申请号：US15496887
申请日：2017-04-25
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Jinwei Yang , Wenhong Sun , Rakesh Jain , Michael Shur , Remigijus Gaska
IPC: H01L29/15 , H01L31/0256 , H01L21/308 , H01L29/66 , H01L21/02 , H01L33/12 , H01L29/20 , H01L33/00
Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
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公开(公告)号：US10199535B2
公开(公告)日：2019-02-05
申请号：US15391994
申请日：2016-12-28
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Jinwei Yang , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
IPC: H01L33/12 , H01L33/32 , H01L33/06 , H01L33/46 , H01L33/00 , C30B29/40 , G06F17/50 , H01L33/14 , H01L33/40
Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.
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公开(公告)号：US10050174B2
公开(公告)日：2018-08-14
申请号：US15457088
申请日：2017-03-13
Applicant: Sensor Electronic Technology, Inc.
Inventor： Michael Shur , Maxim S. Shatalov , Alexander Dobrinsky , Remigijus Gaska , Jinwei Yang
Abstract: A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.
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公开(公告)号：US20180108806A1
公开(公告)日：2018-04-19
申请号：US15857853
申请日：2017-12-29
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Wenhong Sun , Jinwei Yang , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
CPC classification number: H01L33/06 , H01L21/0242 , H01L21/0243 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/0265 , H01L29/0688 , H01L29/2003 , H01L29/518 , H01L29/7786 , H01L33/007 , H01L33/12 , H01L33/20 , H01L33/22 , H01L33/24 , H01L33/32 , H01L2933/0083 , H01L2933/0091
Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
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公开(公告)号：US09923117B2
公开(公告)日：2018-03-20
申请号：US14984156
申请日：2015-12-30
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Alexander Dobrinsky , Alexander Lunev , Rakesh Jain , Jinwei Yang , Michael Shur , Remigijus Gaska
CPC classification number: H01L33/10 , H01L33/007 , H01L33/12 , H01L33/32 , H01L33/46
Abstract: A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher. In one embodiment, the semiconductor layer is used to form an optoelectronic device.
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Patent Agency Ranking
公开(公告)号：US20180026157A1
公开(公告)日：2018-01-25
申请号：US15706990
申请日：2017-09-18
Applicant: Sensor Electronic Technology, Inc.
Inventor： Remigijus Gaska , Maxim S. Shatalov , Alexander Dobrinsky , Jinwei Yang , Michael Shur , Grigory Simin
CPC classification number: H01L33/22 , H01L21/02496 , H01L24/05 , H01L24/14 , H01L29/151 , H01L33/30 , H01L33/32 , H01L33/38 , H01L2224/0401 , H01L2224/06102 , H01L2224/1134 , H01L2924/12041 , H01L2924/12042 , H01L2933/0016 , H01L2924/00
Abstract: A device including a first semiconductor layer and a contact to the first semiconductor layer is disclosed. An interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height and a characteristic width. The characteristic height can correspond to an average vertical distance between crests and adjacent valleys in the first roughness profile. The characteristic width can correspond to an average lateral distance between the crests and adjacent valleys in the first roughness profile.
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公开(公告)号：US09768357B2
公开(公告)日：2017-09-19
申请号：US15042433
申请日：2016-02-12
Applicant: Sensor Electronic Technology, Inc.
Inventor： Remigijus Gaska , Maxim S. Shatalov , Alexander Dobrinsky , Jinwei Yang , Michael Shur , Grigory Simin
CPC classification number: H01L33/405 , H01L24/05 , H01L33/007 , H01L33/0095 , H01L33/06 , H01L33/22 , H01L33/32 , H01L33/38 , H01L2224/0401 , H01L2224/06102 , H01L2224/1134 , H01L2924/12041 , H01L2924/12042 , H01L2933/0016 , H01L2924/00
Abstract: A device including a first semiconductor layer and a contact to the first semiconductor layer is disclosed. An interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height and a characteristic width. The characteristic height can correspond to an average vertical distance between crests and adjacent valleys in the first roughness profile. The characteristic width can correspond to an average lateral distance between the crests and adjacent valleys in the first roughness profile.
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公开(公告)号：US20170229611A1
公开(公告)日：2017-08-10
申请号：US15496887
申请日：2017-04-25
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Jinwei Yang , Wenhong Sun , Rakesh Jain , Michael Shur , Remigijus Gaska
IPC: H01L33/12 , H01L21/02 , H01L21/308
CPC classification number: H01L21/308 , H01L21/0237 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L21/02639 , H01L21/0265 , H01L29/158 , H01L29/2003 , H01L29/66075 , H01L33/007 , H01L33/12
Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
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公开(公告)号：US09705032B2
公开(公告)日：2017-07-11
申请号：US15069249
申请日：2016-03-14
Applicant: Sensor Electronic Technology, Inc.
Inventor： Michael Shur , Remigijus Gaska , Jinwei Yang , Alexander Dobrinsky
CPC classification number: H01L33/06 , H01L33/025 , H01L33/04 , H01L33/10 , H01L33/14 , H01L33/32 , H01L33/325
Abstract: A carbon doped short period superlattice is provided. A heterostructure includes a short period superlattice comprising a plurality of quantum wells alternating with a plurality of barriers. One or more of the quantum wells and/or the barriers includes a carbon doped layer (e.g., a non-percolated or percolated carbon atomic plane).
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公开(公告)号：US20170110628A1
公开(公告)日：2017-04-20
申请号：US15391994
申请日：2016-12-28
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Jinwei Yang , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
IPC: H01L33/12 , H01L33/32 , H01L33/06 , C30B29/40 , H01L33/62 , H01L33/46 , H01L33/00 , H01L33/14 , H01L33/40
CPC classification number: H01L33/12 , C30B29/403 , G06F17/505 , H01L33/007 , H01L33/0075 , H01L33/06 , H01L33/145 , H01L33/32 , H01L33/405 , H01L33/46
Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.
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