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    MILLIMETER WAVE CHIP SCALE ATOMIC CLOCK
    101.
    发明申请
    MILLIMETER WAVE CHIP SCALE ATOMIC CLOCK 审中-公开

    公开(公告)号：US20200241480A1

    公开(公告)日：2020-07-30

    申请号：US16844819

    申请日：2020-04-09

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Bichoy Bahr ,  Argyrios Dellis ,  Juan Alejandro Herbsommer ,  Baher Haroun

    IPC: G04F5/14 ,  H03B17/00 ,  H03L7/26 ,  H03L7/099 ,  G06F1/08

    Abstract: A clock generator includes a hermetically sealed cavity and clock generation circuitry. A dipolar molecule that exhibits a quantum rotational state transition at a fixed frequency is disposed in the cavity. The clock generation circuitry is configured to generate an output clock signal based on the fixed frequency of the dipolar molecule. The clock generation circuitry includes a detector circuit, a multiplier, and reference oscillator control circuitry. The detector circuit is coupled to the cavity, and is configured to generate a detection signal representative of an amplitude of a signal at an output of the cavity. The multiplier is coupled to the detector circuit, and is configured to multiply the detection signal with a mixing signal to produce a derivative of the detection signal. The reference oscillator control circuitry is configured to set a frequency of a reference oscillator based on the derivative of the detection signal.

    Low loss galvanic isolation circuitry
    102.
    发明授权
    Low loss galvanic isolation circuitry 有权

    公开(公告)号：US10523175B2

    公开(公告)日：2019-12-31

    申请号：US15466961

    申请日：2017-03-23

    Applicant: Texas Instruments Incorporated

    Inventor： Swaminathan Sankaran ,  Bradley Allen Kramer ,  Baher Haroun

    IPC: H01P5/02 ,  H03H7/03 ,  H03H7/01 ,  H03H7/09

    Abstract: Disclosed examples include digital isolator modules, isolation circuitry and low-loss multi-order bandpass filter circuits, including a capacitive coupled galvanic isolation circuit with first and second coupling capacitors individually including a first plate and a second plate, and a bond wire connecting the first plates of the coupling capacitors, a first circuit with a first inductor coupled to form a first resonant tank circuit with a first parasitic capacitor associated with the second plate of the first coupling capacitor, and a second circuit with a second inductor coupled to form a second resonant tank circuit with a second parasitic capacitor associated with the second plate of the second coupling capacitor.

    Device and method for on-chip mechanical stress sensing
    104.
    发明授权
    Device and method for on-chip mechanical stress sensing 有权

    公开(公告)号：US10352792B2

    公开(公告)日：2019-07-16

    申请号：US15649934

    申请日：2017-07-14

    Applicant: Texas Instruments Incorporated

    Inventor： Umidjon Nurmetov ,  Ralf Peter Brederlow ,  Baher Haroun

    IPC: G01L1/22 ,  H01L27/06 ,  G01L1/16 ,  H01L29/84 ,  G01L5/16 ,  H01L27/22 ,  G01L25/00 ,  H01L29/8605

    Abstract: An integrated circuit (IC) chip includes a substrate of a piezo-electric material having a first resistivity coefficient associated with a first direction that is longitudinal to a first crystal axis and a second resistivity coefficient associated with a second direction that is transverse to the first crystal axis. The first and second resistivity coefficients have opposite signs. The IC chip also includes a first stress sensing element formed in the substrate and coupled to pass a first current therethrough. The first stress sensing element includes a first resistor aligned such that the major direction of current flow through the first resistor is in the first direction and a second resistor coupled in series with the first resistor and aligned such that the major direction of current flow through the second resistor is in the second direction. A ratio of the resistance of the second resistor to the resistance of the first resistor is equal to a value α, where α is equal to the ratio of the first resistivity coefficient to the second resistivity coefficient.

    Class-E outphasing power amplifier with efficiency and output power enhancement circuits and method
    108.
    发明授权
    Class-E outphasing power amplifier with efficiency and output power enhancement circuits and method 有权

    公开(公告)号：US10250192B2

    公开(公告)日：2019-04-02

    申请号：US15708168

    申请日：2017-09-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Aritra Banerjee ,  Joonhoi Hur ,  Baher Haroun ,  Nathan Richard Schemm ,  Rahmi Hezar ,  Lei Ding

    IPC: H03F3/217 ,  H03F1/02 ,  H03F3/193 ,  H03F3/21 ,  H03F3/45

    Abstract: An outphasing amplifier includes a first class-E power amplifier having an output coupled to a first conductor and an input receiving a first RF drive signal. A first reactive element is coupled between the first conductor and a second conductor. A second reactive element is coupled between the second conductor and a third conductor. A second class-E power amplifier includes an output coupled to a fourth conductor and an input coupled to a second RF drive signal, a third reactive element coupled between the second and fourth conductors. Outputs of the first and second power amplifiers are combined by the first, second and third reactive elements to produce an output current in a load. An efficiency enhancement circuit is coupled between the first and fourth conductors to improve power efficiency at back-off power levels. Power enhancement circuits are coupled to the first and fourth conductors, respectively.

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