公开(公告)号：US20250017113A1

公开(公告)日：2025-01-09

申请号：US18886687

申请日：2024-09-16

Applicant: Texas Instruments Incorporated

Inventor： Umidjon Nurmetov ,  Ralf Peter Brederlow ,  Baher Haroun ,  Jose Antonio Vieira Formenti ,  Michael Szelong ,  Tobias Bernhard Fritz

IPC: H10N30/30 ,  G01L1/18 ,  G01L1/22 ,  H10N30/80

Abstract: In described examples, a circuit includes a substrate and a first resistor on the substrate, the first resistor in a first direction. The circuit also includes a second resistor on the substrate, the second resistor coupled to the first resistor, the second resistor in a second direction, the second direction and the first direction transversely oriented and a device on the substrate.

公开(公告)号：US12154992B2

公开(公告)日：2024-11-26

申请号：US17402287

申请日：2021-08-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rahmi Hezar ,  Henry Litzmann Edwards ,  Miaad Aliroteh ,  Srinath Mathur Ramaswamy ,  Baher Haroun ,  Gerd Schuppener

IPC: H01L31/02 ,  G01S7/4861 ,  H01L31/107

Abstract: A sensor chip includes a sensor pixel. The sensor pixel includes an avalanche photodetector. A circuit is adjacent to the avalanche photodetector. The circuit is coupled to the avalanche photodetector. An isolation structure at least partially encloses the circuit and is between the avalanche photodetector and the circuit.

公开(公告)号：US20240030900A1

公开(公告)日：2024-01-25

申请号：US17872841

申请日：2022-07-25

Applicant: Texas Instruments Incorporated

Inventor： Srijan Rastogi ,  Sumantra Seth ,  Baher Haroun

IPC: H03K3/01 ,  H03F3/45

CPC classification number: H03K3/01 ,  H03F3/45475

Abstract: A driver system includes a non-inverting system input, an inverting system input, a non-inverting system output and an inverting system output. The driver system includes a line driver which includes a non-inverting driver input coupled to the non-inverting system input and includes an inverting driver input coupled to the inverting system input. The line driver includes an inverting driver output and a non-inverting driver output. The driver system includes a first termination resistor coupled between the non-inverting driver output and the non-inverting system output and includes a second termination resistor coupled between the inverting driver output and the inverting system output. The driver system includes a first amplifier stage coupled to the line driver and includes a second amplifier stage coupled to the line driver.

公开(公告)号：US11716056B2

公开(公告)日：2023-08-01

申请号：US17109763

申请日：2020-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tolga Dinc ,  Sachin Kalia ,  Swaminathan Sankaran ,  Baher Haroun

IPC: H03F9/00 ,  H03F1/02 ,  H03F3/45

CPC classification number: H03F1/02 ,  H03F3/45475 ,  H03F2200/09 ,  H03F2200/541

Abstract: A system includes a first differential amplifier and a first transformer with a primary coil coupled to an output of the first differential amplifier and with a secondary coil coupled to a load. The system also includes a second differential amplifier and a second transformer with a primary coil coupled to an output of the second differential amplifier and with a secondary coil coupled in series with the secondary coil of the first transformer. The system also includes a tuning network coupled to a center tap node between the secondary coil of the first transformer and the secondary coil of the second transformer.

公开(公告)号：US11460551B2

公开(公告)日：2022-10-04

申请号：US16287411

申请日：2019-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Baher Haroun ,  Rahmi Hezar ,  Srinath Ramaswamy ,  Nirmal C. Warke ,  David Magee ,  Ting Li

IPC: G01S7/481 ,  G01S17/10 ,  G01S7/4865 ,  G01S7/484

Abstract: A pulsed light source illuminates a scene with a virtual array of points. Light reflected by the scene is detected by a small pixel array, allowing generation of a three-dimensional map of the scene. A processing element processing data output by the small pixel array uses a multipath resolution algorithm to resolve individual objects in the scene.

公开(公告)号：US11342928B1

公开(公告)日：2022-05-24

申请号：US17460575

申请日：2021-08-30

Applicant: Texas Instruments Incorporated

Inventor： Bichoy Bahr ,  Baher Haroun ,  Swaminathan Sankaran ,  Juan Alejandro Herbsommer

IPC: H03L7/197 ,  H03L7/081 ,  H03L7/099 ,  H03L7/093

Abstract: A method, providing an oscillator output signal to reference inputs of a PLL and an output clock circuit; providing a first divisor value to a control input of the PLL to regulate a closed loop that includes a physics cell, a receiver, and the PLL; providing a second divisor value to a control input of the output clock circuit to control an output frequency of an output clock signal; shifting the first divisor value in a first direction to cause a perturbation in the closed loop; shifting the second divisor value in an opposite second direction to counteract a response of the closed loop to the perturbation and to regulate the output frequency of the output clock signal; and based on the receiver output signal, analyzing the response of the closed loop to the perturbation.

公开(公告)号：US20210065830A1

公开(公告)日：2021-03-04

申请号：US17003185

申请日：2020-08-26

Applicant: Texas Instruments Incorporated

Inventor： Ashwin Raghunathan ,  Marco Corsi ,  Baher Haroun ,  Seyed Miaad Seyed Aliroteh ,  Swaminathan Sankaran ,  Robert Floyd Payne

IPC: G11C27/02 ,  H03M1/06 ,  H03M1/12

Abstract: A track and hold circuit includes a signal input terminal, a clock input terminal, an output terminal, a transistor, and a bootstrapping circuit with a transformer. The transistor includes a source, a drain, and a gate, where the source is coupled to the signal input terminal, and the drain is coupled to the output terminal. The transformer includes a primary winding coupled to the clock input terminal, and a secondary winding. The secondary winding is coupled between the source and the gate to control a gate-source voltage of the transistor.

公开(公告)号：US20210044300A1

公开(公告)日：2021-02-11

申请号：US17080879

申请日：2020-10-27

Applicant: Texas Instruments Incorporated

Inventor： Baher Haroun ,  Wenting Zhou ,  Kai Yiu Tam ,  Reza Hoshyar ,  Ali Kiaei

IPC: H03L7/16 ,  H03K23/00

Abstract: A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

公开(公告)号：US20200212899A1

公开(公告)日：2020-07-02

申请号：US16585155

申请日：2019-09-27

Applicant: Texas Instruments Incorporated

Inventor： Tolga Dinc ,  Salvatore Luciano Finocchiaro ,  Gerd Schuppener ,  Siraj Akhtar ,  Swaminathan Sankaran ,  Baher Haroun

IPC: H03K5/02 ,  G01R25/04 ,  H03H7/01 ,  H03K5/26

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to provide phase imbalance correction. An example system includes a phase detector to obtain a first signal and generate a first output, a comparator coupled to the phase detector, the comparator to generate a second output based on the first output, and an amplifier coupled to the comparator, the amplifier to adjust a first phase response of the first signal based on the second output.

公开(公告)号：US10547438B2

公开(公告)日：2020-01-28

申请号：US15858537

申请日：2017-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Baher Haroun ,  Tobias Bernhard Fritz

IPC: H04L7/027 ,  H04J3/06 ,  G05B15/02

Abstract: A circuit includes a serializer module that includes an input stage that samples an input signal to capture an edge location for each of the input signal in a given time frame. An edge encoder encodes the edge location for the input signal into a packet frame to specify where the edge location occurs in the given time frame for the input signal. A transmitter receives the packet frame from the edge decoder and converts the packet frame into a serial data stream. The transmitter communicates the edge location for the input signal via the serial data stream.