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公开(公告)号：US11711916B2
公开(公告)日：2023-07-25
申请号：US17161685
申请日：2021-01-29
Inventor： Yi-Wei Chen , Hsu-Yang Wang , Chun-Chieh Chiu , Shih-Fang Tzou
IPC: H10B12/00 , H01L21/768
CPC classification number: H10B12/485 , H01L21/76804 , H01L21/76805 , H01L21/76814 , H01L21/76819 , H01L21/76895 , H10B12/053 , H10B12/482
Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
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公开(公告)号：US20220271037A1
公开(公告)日：2022-08-25
申请号：US17741431
申请日：2022-05-10
Inventor： Luo-Hsin Lee , Ting-Pang Chung , Shih-Han Hung , Po-Han Wu , Shu-Yen Chan , Shih-Fang Tzou
IPC: H01L27/108 , H01L49/02
Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.
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103.发明授权公开(公告)号：US11239243B2
公开(公告)日：2022-02-01
申请号：US16866573
申请日：2020-05-05
Inventor： Chih-Chieh Tsai , Pin-Hong Chen , Tzu-Chieh Chen , Tsun-Min Cheng , Yi-Wei Chen , Hsin-Fu Huang , Chi-Mao Hsu , Shih-Fang Tzou
IPC: H01L27/108
Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.
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公开(公告)号：US20210202492A1
公开(公告)日：2021-07-01
申请号：US17202359
申请日：2021-03-16
Inventor： Hsu-Yang Wang , Ping-Cheng Hsu , Shih-Fang Tzou , Chin-Lung Lin , Yi-Hsiu Lee , Koji Taniguchi , Harn-Jiunn Wang , Tsung-Ying Tsai
IPC: H01L27/108 , H01L21/308 , H01L21/762
Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.
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公开(公告)号：US11049863B2
公开(公告)日：2021-06-29
申请号：US15889182
申请日：2018-02-05
Inventor： Li-Wei Feng , Shih-Fang Tzou , Chien-Ting Ho , Ying-Chiao Wang , Yu-Ching Chen , Hui-Ling Chuang , Kuei-Hsuan Yu
IPC: H01L27/108
Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.
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Patent Agency Ranking
公开(公告)号：US10861855B2
公开(公告)日：2020-12-08
申请号：US16841702
申请日：2020-04-07
Inventor： Li-Wei Feng , Shih-Fang Tzou , Chien-Cheng Tsai , Chih-Chi Cheng , Chia-Wei Wu , Ger-Pin Lin
IPC: H01L27/108
Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.
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公开(公告)号：US10700071B1
公开(公告)日：2020-06-30
申请号：US16258657
申请日：2019-01-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Gang-Yi Lin , Shih-Fang Tzou , Fu-Che Lee , Feng-Yi Chang , Ying-Chih Lin , Kai-Lou Huang , Yi-Ching Chang
IPC: H01L21/033 , H01L21/308 , H01L27/108
Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.
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公开(公告)号：US10665594B2
公开(公告)日：2020-05-26
申请号：US16036908
申请日：2018-07-16
Inventor： Li-Wei Feng , Ying-Chiao Wang , Shih-Fang Tzou
IPC: H01L29/49 , H01L27/108 , H01L23/535 , H01L29/423 , H01L29/66
Abstract: A semiconductor memory device includes a semiconductor substrate, a gate structure, a first spacer structure, and a gate connection structure. The semiconductor substrate includes a memory cell region and a peripheral region. The gate structure is disposed on the semiconductor substrate and disposed on the peripheral region. The gate structure includes a first conductive layer and a gate capping layer. The gate capping layer is disposed on the first conductive layer. The first spacer structure is disposed on a sidewall of the first conductive layer and a sidewall of the gate capping layer. The gate connection structure includes a first part and a second part. The first part penetrates the gate capping layer and is electrically connected with the first conductive layer. The second part is connected with the first part, and the second part is disposed on and contacts a top surface of the gate capping layer.
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公开(公告)号：US20200105764A1
公开(公告)日：2020-04-02
申请号：US16175858
申请日：2018-10-31
Inventor： Wei-Lun Hsu , Gang-Yi Lin , Yu-Hsiang Hung , Ying-Chih Lin , Feng-Yi Chang , Ming-Te Wei , Shih-Fang Tzou , Fu-Che Lee , Chia-Liang Liao
IPC: H01L27/108 , G11C11/402 , H01L23/538
Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.
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公开(公告)号：US20190341388A1
公开(公告)日：2019-11-07
申请号：US16001949
申请日：2018-06-07
Inventor： Yi-Wei Chen , Hsu-Yang Wang , Chun-Chieh Chiu , Shih-Fang Tzou
IPC: H01L27/108 , H01L21/768
Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
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