公开(公告)号：WO2006117196A3

公开(公告)日：2006-11-09

申请号：PCT/EP2006/004109

申请日：2006-05-03

Applicant: STMICROELECTRONICS S.R.L. ,  VINCIGUERRA, Vincenzo ,  BEVILACQUA, Maria Fortuna ,  BUONOCORE, Francesco ,  COFFA, Salvatore

Inventor： VINCIGUERRA, Vincenzo ,  BEVILACQUA, Maria Fortuna ,  BUONOCORE, Francesco ,  COFFA, Salvatore

IPC: C01B31/02 ,  H01L21/768

Abstract: Method for growing carbon nanotubes having a determined chirality, comprising the steps of fragmentation of at least one initial carbon nanotube (30) having a determined chirality with obtainment of at least two portions, or seeds, of carbon nanotube, each one having one free growth end (32); supply of atoms of carbon (33) with autocatalyst addition of the atoms of carbon (33) at the free end (32) of each portion of nanotube (30) to determine an elongation, or growth, of the nanotube (30).

公开(公告)号：WO2006103246A1

公开(公告)日：2006-10-05

申请号：PCT/EP2006/061116

申请日：2006-03-28

Applicant: STMICROELECTRONICS S.R.L. ,  TRONCONI, Michele ,  CHIESA, Enrico ,  PASOLINI, Fabio

Inventor： TRONCONI, Michele ,  CHIESA, Enrico ,  PASOLINI, Fabio

IPC: H03H17/04

CPC classification number: H03H17/04 ,  G01P15/0891 ,  G01P15/18

Abstract: A digital high-pass filter (12) has an input (IN), an output (OUT), and a subtractor stage (20), having a first input terminal, a second input terminal and an output terminal. The first input terminal of the subtractor stage (20) is connected to the input (IN) of the digital high-pass filter (12) and the output terminal is connected to the output (OUT) of the digital high-pass filter (12). A recursive circuit branch (21) is connected between the output (OUT) of the digital high-pass filter (12) and the second input terminal of the subtractor stage (20). Within the recursive circuit branch (21) are cascaded an accumulation stage (23), constituted by an integrator circuit, and a divider stage (24). The cutoff frequency (f t ) of the digital high-pass filter (12) is variable according to a dividing factor (den) of the divider stage (24).

Abstract translation: 数字高通滤波器（12）具有输入（IN），输出（OUT）和减法器级（20），具有第一输入端，第二输入端和输出端。 减法器级（20）的第一输入端连接到数字高通滤波器（12）的输入（IN），输出端连接到数字高通滤波器（12）的输出端 ）。 递归电路分支（21）连接在数字高通滤波器（12）的输出（OUT）和减法器级（20）的第二输入端之间。 在递归电路分支（21）内，级联由积分器电路和分频器级（24）构成的累加级（23）。 数字高通滤波器（12）的截止频率（f ）根据分频器级（24）的分频因子（den）而变化。

公开(公告)号：WO2006089725A3

公开(公告)日：2006-08-31

申请号：PCT/EP2006/001591

申请日：2006-02-22

Applicant: STMICROELECTRONICS S.R.L. ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

IPC: H01L29/78

Abstract: Power semiconductor device (30) integrated on a semiconductor substrate (100) of a first type of conductivity comprising a plurality of elemental units, each elemental unit comprising a body region (40) of a second type of conductivity realised on a semiconductor layer (20) of the first type of conductivity formed on the semiconductor substrate (100), and a column region (50) of the first type of conductivity realised in said semiconductor layer (20) below the body region (40), wherein the semiconductor layer (20) comprises a plurality of semiconductor layers (21, 22, 23, 24), overlying each other, the resistivity of each layer being different from that of the other layers, and wherein said column region (50) comprises a plurality of doped sub-regions (51, 52, 53, 54), each realised in one of said semiconductor layers (21, 22, 23, 24), wherein the amount of charge of each doped sub-regions (51, 52, 53, 54) balances the amount of charge of the semiconductor layer (21, 22, 23, 24).

公开(公告)号：WO2006069933A1

公开(公告)日：2006-07-06

申请号：PCT/EP2005/056921

申请日：2005-12-19

Applicant: STMICROELECTRONICS S.R.L. ,  KARPOV, Ilya, V. ,  KUO, Charles C. ,  KIM, Yudong ,  ATWOOD, Greg

Inventor： KARPOV, Ilya, V. ,  KUO, Charles C. ,  KIM, Yudong ,  ATWOOD, Greg

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/04 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1683

Abstract: Both a chalcogenide select device (24, 120) and a chalcogenide memory element (40, 130) are formed within vias within dielectrics (18, 22). As a result, the chalcogenides is effectively trapped within the vias and no glue or adhesion layer is needed. Moreover, delamination problems are avoided. A lance material (30) is formed within the same via (31) with the memory element (40, 130). In one embodiment, the lance material is made thinner by virtue of the presence of a sidewall spacer (28); in another embodiment no sidewall spacer is utilized. A relatively small area of contact between the chalcogenide (40) used to form a memory element (130) and the lance material (30) is achieved by providing a pin hole opening in a dielectric (34), which separates the chalcogenide and the lance material.

Abstract translation: 在电介质（18,22）内的通孔内形成硫族化物选择装置（24,120）和硫族化物存储元件（40,130）。 结果，硫属化物被有效地捕获在通孔内，并且不需要胶或粘合层。 此外，避免了分层问题。 在与存储元件（40,130）相同的通孔（31）内形成喷枪材料（30）。 在一个实施例中，由于存在侧壁间隔件（28），喷枪材料制成更薄。 在另一个实施例中，没有使用侧壁间隔物。 用于形成存储元件（130）的硫族化物（40）与喷枪材料（30）之间的相对小的接触面积是通过在电介质（34）中设置一个销孔开口来实现的，所述电极隔开硫族化物和喷枪 材料。

公开(公告)号：WO2006067563A1

公开(公告)日：2006-06-29

申请号：PCT/IB2005/003606

申请日：2005-11-28

Applicant: STMICROELECTRONICS S.r.l. ,  POLONI, Angelo ,  SILVA, Filippo ,  VALLE, Stefano

Inventor： POLONI, Angelo ,  SILVA, Filippo ,  VALLE, Stefano

IPC: H04L25/02

CPC classification number: H04L25/0216 ,  H04L25/0212 ,  H04L27/2601

Abstract: In order to execute, as a function of a received signal (r), a procedure of channel estimation in a transmission channel with memory in a telecommunications system, there is envisaged an operation of estimation of a delay spread associated to said channel, said operation of estimation comprising calculation of a root mean square value ( τ rms ) of delay spread by means of a step of evaluation of crossings with a threshold level of a quantity associated to a transfer function of said channel. Said step of evaluation of crossings comprises evaluating a mean number of crossings ( λ 0 ) of the real and imaginary parts of said channel transfer function with a threshold level corresponding to the zero level. Preferential application is to OFDM telecommunications systems and in particular wireless. systems according to the IEEE 802.11a WLAN standard or the Hyperlanil WLAN standard.

Abstract translation: 为了根据接收信号（r）执行在电信系统中具有存储器的传输信道中的信道估计的过程，设想了与所述信道相关联的延迟扩展的估计的操作，所述操作 的估计包括计算均方根值（t

公开(公告)号：WO2005107138A1

公开(公告)日：2005-11-10

申请号：PCT/FR2004/050133

申请日：2004-03-29

Applicant: STMicroelectronics SA ,  STMicroelectronics S.r.l. ,  TEGLIA, Yannick ,  ROMAIN, Fabrice ,  LIARDET, Pierre-Yvan ,  FRAGNETO, Pasqualina ,  SOZZANI, Fabio ,  BERTONI, Guido

Inventor： TEGLIA, Yannick ,  ROMAIN, Fabrice ,  LIARDET, Pierre-Yvan ,  FRAGNETO, Pasqualina ,  SOZZANI, Fabio ,  BERTONI, Guido

IPC: H04L9/06

CPC classification number: H04L9/0631 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/08 ,  H04L2209/122

Abstract: L'invention concerne un processeur d'exécution d'un algorithme Rijndeal, effectuant plusieurs tours de chiffrement d'une matrice composée de blocs de données pour obtenir une matrice de même taille, chaque tour impliquant une matrice de blocs de clés et une table de substitution des blocs de données, le processeur comportant : un premier registre d'entrée (102) pour contenir une colonne de blocs de données d'entrée ; un registre de sortie (111) pour contenir une colonne de blocs de données de sortie ou une colonne de blocs intermédiaires ; un deuxième registre d'entrée (101) pour contenir une colonne de blocs de clés ou les blocs de données intermédiaires ; un élément (104) de substitution de blocs recevant les données bloc par bloc après sélection (103) dans le premier registre et fournissant, pour chaque bloc, une colonne de blocs ; un élément (109) de permutation circulaire des blocs de la colonne du circuit de substitution ; et un élément (110) de combinaison OU-Exclusif de la colonne de blocs du circuit de permutation avec le contenu du deuxième registre, le résultat de la combinaison étant chargée dans le registre de sortie.

Abstract translation: 一种用于执行Rijndeal算法的处理器，该Rijndeal算法将多个加密回合应用于数据块阵列，以便获得相同大小的阵列，每轮涉及密钥块阵列和数据块替换表，其中所述处理器包括：第一 输入寄存器（102），其包含输入数据块列; 包含输出数据块列或中间块列的输出寄存器（111）; 包含密钥块列或中间数据块的第二输入寄存器（101）; 块替换元件（104）在第一寄存器中的选择（103）之后的时间接收数据一个块，并为每个块提供一列块; 向替代电路列块施加循环置换的元件（109）; 以及将置换电路列块与第二寄存器的内容组合的异或组合元件（110），所述组合的结果被加载到输出寄存器中。

公开(公告)号：WO2005104223A1

公开(公告)日：2005-11-03

申请号：PCT/EP2005/051694

申请日：2005-04-18

Applicant: STMICROELECTRONICS S.R.L. ,  PONZA, Anna ,  DEPETRO, Riccardo ,  MONTANINI, Pietro

Inventor： PONZA, Anna ,  DEPETRO, Riccardo ,  MONTANINI, Pietro

IPC: H01L21/78

CPC classification number: H01L21/78

Abstract: A process for the fabrication of an integrated device in a semiconductor chip envisages: forming a semiconductor layer (5') partially suspended above a semiconductor substrate (2) and constrained to the substrate (2) by temporary anchorages (10, 15'); dividing the layer (5') into a plurality of portions (13) laterally separated from one another; and removing the temporary anchorages (10, 15'; 38), in order to free the portions (13).

Abstract translation: 用于制造半导体芯片中的集成器件的方法设想：形成半导体衬底（2）部分悬置并通过临时锚固（10,15'）约束到衬底（2）的半导体层（5'）; 将层（5'）分成彼此横向分离的多个部分（13）; 以及移除所述临时锚固件（10,15'; 38），以便释放所述部分（13）。

公开(公告)号：WO2004102671A1

公开(公告)日：2004-11-25

申请号：PCT/IT2003/000298

申请日：2003-05-19

Applicant: STMICROELECTRONICS S.R.L. ,  RONSISVALLE, Cesare

Inventor： RONSISVALLE, Cesare

IPC: H01L29/745

CPC classification number: H01L29/66378 ,  H01L29/7455

Abstract: A power device (1) formed by a thyristor (25) and by a MOSFET transistor (26), series-connected between a first and a second current-conduction terminal (A, S). the power device (1) moreover has a control terminal (G) connected to an insulated-gate electrode (20) of the MOSFET transistor (26) and receiving a control voltage for turning on/off the device, and a third current-conduction terminal (B) connected to the thyristor (25) for fast extraction of charges during turning-off. Thereby, upon turning off, there are no current tails, and turning off is very fast. The power device does not have parasitic components and consequently has a very high reversebias safe-operating area (RBSOA).

Abstract translation: 由晶闸管（25）和串联连接在第一和第二导通端子（A，S）之间的MOSFET晶体管（26）形成的功率器件（1）。 功率器件（1）还具有连接到MOSFET晶体管（26）的绝缘栅电极（20）的控制端子（G），并接收用于接通/关断器件的控制电压和第三电流传导 端子（B）连接到晶闸管（25），用于在关断期间快速提取电荷。 因此，在关闭时，没有当前尾部，并且关闭非常快。 功率器件没有寄生元件，因此具有非常高的反向保护工作区（RBSOA）。

公开(公告)号：WO2004047327A1

公开(公告)日：2004-06-03

申请号：PCT/EP2002/012814

申请日：2002-11-15

Applicant: TELECOM ITALIA S.P.A. ,  STMICROELECTRONICS S.R.L. ,  ETTORRE, Donato ,  GRAZIANO, Maurizio ,  MELIS, Bruno ,  FINOTELLO, Andrea ,  RUSCITTO, Alfredo

Inventor： ETTORRE, Donato ,  GRAZIANO, Maurizio ,  MELIS, Bruno ,  FINOTELLO, Andrea ,  RUSCITTO, Alfredo

IPC: H04B1/707

CPC classification number: H04B1/7085 ,  H04B1/709

Abstract: A device for maintaining fine alignment between an incoming spread spectrum signal and a locally generated code in a digital communication receiver comprises: - a delay line (56) for storing a plurality of consecutive samples (E-1, E, M, L, L+1) of the incoming spread spectrum signal; - three digitally controlled interpolators (24, 26, 28) for determining by interpolation between consecutive samples an interpolated early sample (e), an interpolated middle sample (m) and an interpolated late sample (1); - two correlators (30, 32) for calculating an error signal (ξ) as the difference between the energy of the symbols computed from the interpolated early (e) and late (1) samples; - a circuit for generating a control signal (S¿OUT?) for controlling the interpolation phase of the digitally controlled interpolator (24) for the early sample (e), and - a digital non-linear filter (68), for smoothing the control signal (S¿OUT?) of the interpolator (24) for the early sample (e), enabling the update operation of the control signal only when the absolute value (|ξ(n)|) of the error signal at a time instant n is smaller than the absolute value (|ξ(n-1)|) of the same error signal at a time instant n-1.

Abstract translation: 一种用于在数字通信接收机中保持输入扩频信号与本地生成代码之间的精确对准的装置，包括： - 延迟线（56），用于存储多个连续样本（E-1，E，M，L，L +1）的入射扩频信号; - 三个数字控制内插器（24,26,28），用于通过内插的早期采样（e），内插中间样本（m）和插值后期样本（1）来确定连续采样之间的内插; - 用于计算误差信号（xi）的两个相关器（30,32）作为从内插的早期（e）和晚期（1）样本计算的符号的能量之间的差; - 用于产生用于控制用于早期采样（e）的数字控制内插器（24）的内插相位的控制信号（S _ OUT <）的电路，以及 - 数字非线性滤波器（68），用于平滑 用于早期采样（e）的内插器（24）的控制信号（S _OUT？），使得只有当误差信号的绝对值（|| xi（n）||） 时刻n小于在时刻n-1的相同误差信号的绝对值（|| xi（n-1）||）。

公开(公告)号：WO2003012983A1

公开(公告)日：2003-02-13

申请号：PCT/EP2002/007524

申请日：2002-07-05

Applicant: STMICROELECTRONICS S.R.L. ,  CONFALONIERI, Pierangelo ,  NICOLLINI, Germano ,  MARTIGNONE, Riccardo

Inventor： CONFALONIERI, Pierangelo ,  NICOLLINI, Germano ,  MARTIGNONE, Riccardo

IPC: H03F3/45

CPC classification number: H03F3/45937 ,  H03F1/303

Abstract: The circuit comprises a differential amplifier (10) with two inputs and two outputs and a common mode regulation circuit. Between a regulation terminal (INCM) of the amplifier and the outputs there are connected a first (C1p) and a second (1m) capacitor and first (C3) and second (C4) capacitive means that by means of controlled switches (SW9-SW12) can be alternatively and simultaneousy connected in parallel with, respectively, the first ((C1p) and the second (C1m) capacitor or between a first (VB) and a second (Vref1) reference voltage terminal. The capacitances C3 and C4 may be different in value such as to satisfy the following equality: Vcmn = Vref1 + '(Vrefp-Vrefm)/2!* (C4-C3)/(C3+C4), where Vcmn is the desired common mode output voltage, Vrefp and Vrefm are the differential output voltages and Vref1 is the voltage of the second reference terminal.are chosen in such a way as to satisfy the following equality : Vcmn = Vref1 + [(Vrefp-Vrefm)/2] * (C4-C3)/(C3+C4), where Vcmn is the desired common mode output voltage, Vrefp and Vrefm are the differential output voltages and Vref1 is the voltage of the second reference terminal.

Abstract translation: 该电路包括具有两个输入和两个输出的差分放大器（10）和一个共模调节电路。 在放大器的调节端子（INCM）和输出端之间连接有第一（C1p）和第二（1m）电容器以及通过受控开关（SW9-SW12）的第一（C3）和第二（C4）电容装置 ）可以分别与第一（（C1p）和第二（C1m）电容器或第一（VB）和第二（Vref1）参考电压端子并联连接，电容C3和C4可以是 不同的值，以满足以下等式：Vcmn = Vref1 +'（Vrefp-Vrefm）/ 2！*（C4-C3）/（C3 + C4），其中Vcmn是期望的共模输出电压，Vrefp和Vrefm 是差分输出电压，Vref1是第二参考端子的电压，以满足以下等式的方式选择：Vcmn = Vref1 + [（Vrefp-Vrefm）/ 2] *（C4-C3）/（ C3 + C4），其中Vcmn是所需的共模输出电压，Vrefp和Vrefm是差分输出电压，Vref1是秒的电压 参考端子。