公开(公告)号：US20180096962A1

公开(公告)日：2018-04-05

申请号：US15820907

申请日：2017-11-22

Applicant: EV Group E. Thallner GmbH

Inventor： Andreas Fehkuhrer

IPC: H01L23/00 ,  H01L25/00 ,  B32B37/00 ,  H01L23/544 ,  H01L21/683 ,  H01L21/67 ,  H01L21/304 ,  H01L21/18 ,  B32B38/18 ,  H01L25/065 ,  H01L21/78

CPC classification number: H01L24/80 ,  B32B37/0046 ,  B32B38/1841 ,  B32B38/1858 ,  B32B2309/105 ,  B32B2457/14 ,  H01L21/187 ,  H01L21/304 ,  H01L21/67092 ,  H01L21/6831 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L24/08 ,  H01L24/74 ,  H01L24/75 ,  H01L24/94 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/0224 ,  H01L2224/0381 ,  H01L2224/0382 ,  H01L2224/03831 ,  H01L2224/0384 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/75251 ,  H01L2224/75272 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75704 ,  H01L2224/75705 ,  H01L2224/75724 ,  H01L2224/75725 ,  H01L2224/75734 ,  H01L2224/75735 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/80 ,  H01L2224/80003 ,  H01L2224/80006 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/8002 ,  H01L2224/80047 ,  H01L2224/80051 ,  H01L2224/80093 ,  H01L2224/80099 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80209 ,  H01L2224/80213 ,  H01L2224/80801 ,  H01L2224/80894 ,  H01L2224/80907 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2221/68304

Abstract: A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.

公开(公告)号：US09646860B2

公开(公告)日：2017-05-09

申请号：US13963741

申请日：2013-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Xin-Hua Huang ,  Xiaomeng Chen ,  Ping-Yin Liu ,  Lan-Lin Chao

IPC: H01L21/68 ,  H01L21/67 ,  H01L23/00

CPC classification number: H01L24/94 ,  H01L21/67092 ,  H01L21/681 ,  H01L24/08 ,  H01L24/74 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/753 ,  H01L2224/75702 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75802 ,  H01L2224/75804 ,  H01L2224/75822 ,  H01L2224/75824 ,  H01L2224/759 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80019 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80986 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/80 ,  H01L2924/00015 ,  H01L2224/80121 ,  H01L2924/00

Abstract: Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes means for monitoring an alignment of a first wafer and a second wafer, and means for adjusting a position of the second wafer. The alignment system includes means for feeding back a relative position of the first wafer and the second wafer to the means for adjusting the position of the second wafer before and during a bonding process for the first wafer and the second wafer.

公开(公告)号：US09576827B2

公开(公告)日：2017-02-21

申请号：US14298692

申请日：2014-06-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Liu ,  Yen-Chang Chu ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Ru-Liang Lee

IPC: H01L23/00 ,  H01L21/67 ,  H01L25/00 ,  B23B31/30

CPC classification number: H01L21/67092 ,  B23B31/305 ,  B23B31/307 ,  H01L21/6838 ,  H01L24/75 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/7501 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/80013 ,  H01L2224/8013 ,  H01L2224/80201 ,  H01L2224/80894 ,  H01L2224/94 ,  H01L2225/06593 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/3511 ,  Y10T156/14 ,  H01L2224/80 ,  H01L2224/80001

Abstract: A system for and a method of bonding a first wafer to a second wafer are provided. A second wafer chuck has a second surface, a profile of the second surface being adjustable by a profile control layer. The first wafer is placed on a first surface of a first wafer chuck, and the second wafer is placed on the second surface of the second wafer chuck. The first wafer and the second wafer are warped prior to bonding to form a first warped wafer and a second warped wafer, respectively. The first warped wafer is bonded to the second warped wafer.

Abstract translation: 提供了将第一晶片接合到第二晶片的系统和方法。 第二晶片卡盘具有第二表面，第二表面的轮廓可由轮廓控制层调节。 将第一晶片放置在第一晶片卡盘的第一表面上，并且将第二晶片放置在第二晶片卡盘的第二表面上。 第一晶片和第二晶片在接合之前变形，分别形成第一翘曲晶片和第二翘曲晶片。 第一个翘曲的晶片与第二个翘曲晶片接合。

公开(公告)号：US09437568B2

公开(公告)日：2016-09-06

申请号：US14518389

申请日：2014-10-20

Applicant: Kabushiki Kaisha Toshiba

Inventor： Atsuko Kawasaki

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/76 ,  H01L21/302 ,  H01L21/461 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/24 ,  H01L21/31144 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/215 ,  H01L2224/24146 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/821 ,  H01L2224/96 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/80001

Abstract: Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.

Abstract translation: 某些实施例提供一种用于制造半导体器件的方法，包括形成第一互连层，该第一互连层具有从第一互连层的表面露出的第一导电层和第一绝缘层，形成具有第二导电层的第二互连层和 第二绝缘层，其从第二互连层的表面露出，通过使第一绝缘层的表面的部分区域低于第一绝缘层的表面，在第一绝缘层的表面上形成第一非接合表面 导电层，所述部分区域包含所述第一导电层的周围环境，并且连接所述第一导电层的表面和所述第二导电层的表面，并且将除了所述第一非接合表面和所述表面之外的所述第一绝缘层的表面 的第二绝缘层。

公开(公告)号：US20160133496A1

公开(公告)日：2016-05-12

申请号：US14933694

申请日：2015-11-05

Applicant: SKORPIOS TECHNOLOGIES, INC.

Inventor： Damien Lambert ,  John Spann ,  Stephen Krasulick

IPC: H01L21/683 ,  H01L21/027 ,  H01L23/00

CPC classification number: H01L21/6835 ,  G02B6/4201 ,  H01L21/0274 ,  H01L21/2007 ,  H01L21/683 ,  H01L21/76254 ,  H01L24/03 ,  H01L24/27 ,  H01L24/75 ,  H01L24/83 ,  H01L24/89 ,  H01L24/94 ,  H01L24/95 ,  H01L2221/68313 ,  H01L2221/68318 ,  H01L2221/6834 ,  H01L2221/68354 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/0362 ,  H01L2224/75305 ,  H01L2224/75315 ,  H01L2224/80201 ,  H01L2224/83001 ,  H01L2224/83203 ,  H01L2225/06593 ,  H01L2924/01014 ,  H01L2924/1032 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15738

Abstract: A transfer substrate with a compliant resin is used to bond one or more chips to a target wafer. An implant region is formed in a transfer substrate. A portion of the transfer substrate is etched to form a riser. Compliant material is applied to the transfer substrate. A chip is secured to the compliant material, wherein the chip is secured to the compliant material above the riser. The chip is bonded to a target wafer while the chip is secured to the compliant material. The transfer substrate and compliant material are removed from the chip. The transfer substrate is opaque to UV light.

Abstract translation: 使用具有顺应性树脂的转印衬底将一个或多个芯片结合到目标晶片。 植入区域形成在转印衬底中。 转印衬底的一部分被蚀刻以形成提升器。 将合适的材料施加到转印基板上。 芯片被固定到柔性材料上，其中芯片被固定到提升管上方的柔性材料。 当芯片固定到顺应性材料时，芯片被结合到目标晶片。 从芯片上去除转印衬底和柔顺材料。 转印衬底对UV光是不透明的。

公开(公告)号：US20160043060A1

公开(公告)日：2016-02-11

申请号：US14920289

申请日：2015-10-22

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Tatsuya KABE ,  Hideyuki ARAI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/5223 ,  H01L23/5227 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L27/0688 ,  H01L28/20 ,  H01L28/40 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/08145 ,  H01L2224/80097 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/0132 ,  H01L2924/05042 ,  H01L2924/0534 ,  H01L2924/05442 ,  H01L2924/0549 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor device includes: a first substrate including a first surface layer that includes first and second electrodes; a second substrate including a second surface layer that includes third and fourth electrodes, and directly bonded to the first substrate such that the second surface layer is in contact with the first surface layer; and a functional film provided between the second and fourth electrodes. The first and third electrodes are bonded together so as to be in contact with each other, and the second electrode, the functional film, and the fourth electrode constitute a passive element.

Abstract translation: 一种半导体器件包括：第一衬底，包括包括第一和第二电极的第一表面层; 第二基板，其包括包括第三和第四电极的第二表面层，并且直接接合到第一基板，使得第二表面层与第一表面层接触; 以及设置在第二和第四电极之间的功能膜。 第一和第三电极彼此接触结合在一起，并且第二电极，功能膜和第四电极构成无源元件。

公开(公告)号：US09257399B2

公开(公告)日：2016-02-09

申请号：US14056345

申请日：2013-10-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsun-Chung Kuang ,  Yen-Chang Chu ,  Cheng-Tai Hsiao ,  Ping-Yin Liu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L25/065 ,  H01L25/04 ,  H01L25/075 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L21/76883 ,  H01L21/76805 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/538 ,  H01L23/5385 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/10 ,  H01L24/18 ,  H01L24/80 ,  H01L24/89 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/0756 ,  H01L25/50 ,  H01L2224/03616 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/80097 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2225/06513 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

Abstract translation: 集成电路结构包括封装部件，该封装部件还包括具有第一孔隙率的无孔介电层，以及在无孔介电层上方和与无孔介电层接触的多孔电介质层，其中多孔介电层具有高于 第一孔隙度。 接合垫穿透无孔介电层和多孔介电层。 电介质阻挡层覆盖并与多孔电介质层接触。 接合焊盘通过介电阻挡层露出。 电介质阻挡层具有平坦的顶表面。 接合焊盘具有比介电阻挡层的底表面高的平面顶表面。

公开(公告)号：US20150357226A1

公开(公告)日：2015-12-10

申请号：US14298692

申请日：2014-06-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Liu ,  Yen-Chang Chu ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Ru-Liang Lee

IPC: H01L21/683 ,  H01L21/67 ,  B23B31/30 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L21/67092 ,  B23B31/305 ,  B23B31/307 ,  H01L21/6838 ,  H01L24/75 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/7501 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/80013 ,  H01L2224/8013 ,  H01L2224/80201 ,  H01L2224/80894 ,  H01L2224/94 ,  H01L2225/06593 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/3511 ,  Y10T156/14 ,  H01L2224/80 ,  H01L2224/80001

Abstract: A system for and a method of bonding a first wafer to a second wafer are provided. A second wafer chuck has a second surface, a profile of the second surface being adjustable by a profile control layer. The first wafer is placed on a first surface of a first wafer chuck, and the second wafer is placed on the second surface of the second wafer chuck. The first wafer and the second wafer are warped prior to bonding to form a first warped wafer and a second warped wafer, respectively. The first warped wafer is bonded to the second warped wafer.

Abstract translation: 提供了将第一晶片接合到第二晶片的系统和方法。 第二晶片卡盘具有第二表面，第二表面的轮廓可由轮廓控制层调节。 将第一晶片放置在第一晶片卡盘的第一表面上，并且将第二晶片放置在第二晶片卡盘的第二表面上。 第一晶片和第二晶片在接合之前变形，分别形成第一翘曲晶片和第二翘曲晶片。 第一个翘曲的晶片与第二个翘曲晶片接合。

公开(公告)号：US09142532B2

公开(公告)日：2015-09-22

申请号：US14397038

申请日：2013-04-24

Applicant: Tadatomo Suga ,  BONDTECH CO., LTD.

Inventor： Tadatomo Suga ,  Akira Yamauchi

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  B23K31/02 ,  B23K37/00 ,  B23K37/04 ,  H01L21/66 ,  H01L25/10 ,  H01L23/10 ,  H01L21/683

CPC classification number: H01L25/0652 ,  B23K31/02 ,  B23K37/00 ,  B23K37/0408 ,  B23K2101/40 ,  H01L21/6836 ,  H01L22/10 ,  H01L23/10 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/74 ,  H01L24/742 ,  H01L24/743 ,  H01L24/75 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06134 ,  H01L2224/0615 ,  H01L2224/06177 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/09181 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13009 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14134 ,  H01L2224/1415 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/27009 ,  H01L2224/2755 ,  H01L2224/27823 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73103 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/75102 ,  H01L2224/7525 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75283 ,  H01L2224/753 ,  H01L2224/75301 ,  H01L2224/7531 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/7565 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75753 ,  H01L2224/75802 ,  H01L2224/75804 ,  H01L2224/75824 ,  H01L2224/75842 ,  H01L2224/7598 ,  H01L2224/80003 ,  H01L2224/8001 ,  H01L2224/80013 ,  H01L2224/80065 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80143 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/8022 ,  H01L2224/8023 ,  H01L2224/80447 ,  H01L2224/8083 ,  H01L2224/80907 ,  H01L2224/81002 ,  H01L2224/8101 ,  H01L2224/81013 ,  H01L2224/81065 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/8122 ,  H01L2224/8123 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81805 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2224/83002 ,  H01L2224/8301 ,  H01L2224/83013 ,  H01L2224/83048 ,  H01L2224/83051 ,  H01L2224/83065 ,  H01L2224/83091 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83136 ,  H01L2224/83143 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/8322 ,  H01L2224/8323 ,  H01L2224/83234 ,  H01L2224/83355 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2224/83894 ,  H01L2224/83907 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2924/00

Abstract: [Problem] Provided is a technique for bonding chips efficiently onto a wafer to establish an electrical connection and raise mechanical strength between the chips and the wafer or between the chips that are chips laminated onto each other in the state that resin and other undesired residues do not remain on a bond interface therebetween.[Solution] A method for bonding plural chips each having a chip-side-bond-surface having metal regions to a substrate having plural bond portions has the step (S1) of subjecting the metal regions of the chip-side-bond-surface to surface activating treatment and hydrophilizing treatment; the step (S2) of subjecting the bond portions of the substrate to surface activating treatment and hydrophilizing treatment; the step (S3) of fitting the chips subjected to the surface activating treatment and the hydrophilizing treatment onto the corresponding bond portions of the substrate subjected to the surface activating treatment and the hydrophilizing treatment to bring the metal regions of the chips into contact with the bond portions of the substrate; and the step (S4) of heating the resultant structure, which includes the substrate, and the chips fitted onto the substrate.

Abstract translation: [问题]提供了一种将芯片有效地接合到晶片上以建立电连接并提高芯片和晶片之间或芯片之间的机械强度的技术，该芯片是在树脂和其它不期望的残留物的状态下彼此层压的芯片 不保留在它们之间的结合界面上。 [解决方案]将具有金属区域的具有芯片侧接合面的多个芯片接合到具有多个结合部的基板的方法具有将芯片侧接合面的金属区域 表面活化处理和亲水处理; 对所述基板的所述接合部进行表面活化处理和亲水化处理的工序（S2） 将经过表面活化处理和亲水化处理的芯片装配到经过表面活化处理的基板的相应接合部分和亲水化处理上以使芯片的金属区域与键接触的步骤（S3） 基板的一部分; 以及加热包括基板的所得结构和安装在基板上的芯片的步骤（S4）。

公开(公告)号：US20150162294A1

公开(公告)日：2015-06-11

申请号：US14518389

申请日：2014-10-20

Applicant: Kabushiki Kaisha Toshiba

Inventor： Atsuko KAWASAKI

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L24/24 ,  H01L21/31144 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/215 ,  H01L2224/24146 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/821 ,  H01L2224/96 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/80001

Abstract: Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.

Abstract translation: 某些实施例提供一种用于制造半导体器件的方法，包括形成第一互连层，该第一互连层具有从第一互连层的表面露出的第一导电层和第一绝缘层，形成具有第二导电层的第二互连层和 第二绝缘层，其从第二互连层的表面露出，通过使第一绝缘层的表面的部分区域低于第一绝缘层的表面，在第一绝缘层的表面上形成第一非接合表面 导电层，所述部分区域包含所述第一导电层的周围环境，并且连接所述第一导电层的表面和所述第二导电层的表面，并且将除了所述第一非接合表面和所述表面之外的所述第一绝缘层的表面 的第二绝缘层。