公开(公告)号：WO1994015332A1

公开(公告)日：1994-07-07

申请号：PCT/FR1993001277

申请日：1993-12-21

Applicant: THOMSON-CSF ,  THOMSON CONSUMER ELECTRONICS ,  MAURICE, François ,  SONRIER, Michel ,  PIROT, François-Xavier

Inventor： THOMSON-CSF ,  THOMSON CONSUMER ELECTRONICS

IPC: G11B05/09

CPC classification number: G11B5/00817 ,  G11B5/00813 ,  G11B5/00821 ,  G11B5/02 ,  G11B5/09 ,  G11B5/4976

Abstract: Process and system for the magnetic recording of data on several parallel tracks, whereby data is recorded on a track by induction of a magnetic field having a given direction in an area of said track. During said recording, a magnetic field having an opposite direction is induced in adjacent track areas. For this purpose, the winding (L0, L1, L2) of each head is coupled to at least the windings (L0, L1, L2) of the adjacent heads. A control current transmitted to said head thereby produces at least one derived current which goes to adjacent heads. Application in the correction of crosstalk during reading of high density magnetic recordings.

Abstract translation: 用于在几个平行轨道上磁记录数据的处理和系统，由此通过在所述轨道的区域中感应具有给定方向的磁场来将数据记录在轨道上。 在所述记录期间，在相邻轨道区域中产生具有相反方向的磁场。 为此，每个磁头的绕组（L0，L1，L2）至少耦合到相邻磁头的绕组（L0，L1，L2）。 传输到所述磁头的控制电流从而产生至少一个到达相邻磁头的导出电流。 在高密度磁记录读取期间纠正串扰的应用。

公开(公告)号：WO1993014493A1

公开(公告)日：1993-07-22

申请号：PCT/JP1992001694

申请日：1992-12-25

Applicant: FUJITSU LIMITED ,  KANEGAE, Masahide

Inventor： FUJITSU LIMITED

IPC: G11B05/09

CPC classification number: G11B20/10046 ,  A63C17/064 ,  A63C17/226 ,  G11B5/035 ,  G11B5/09 ,  G11B20/10009

Abstract: A circuit for equalizing the waveform of signal reproduced by a thin film magnetic head, which removes the negative edge of the waveform regardless of variation of the characteristics of the heads. In the equalizing circuit, an arithmetic circuit (7) receives the inputted read-out signal including negative edges and outputted from a thin film magnetic head, and equalizes the waveform of the inputted signal of a selected head (1) among thin film magnetic heads, using the following three output signals: the output of delay circuits (2, 3) whose input sides are terminated by means of characteristic impedances and which delay the inputted signal by a time tau 2, the output of a multiplying circuit (4) for multiplying the signal which is delayed by a time ( tau 2 - tau 1) by a value K1, and the output of a variable delay-time circuit (6) for delaying the inputted signal so as to remove the negative edges. The equalizing circuit is further provided with a delay setting circuit (8) which sets the delay time of the variable delay-time circuit (6) according to the signal representing the position of the head (1) and the head selecting signal. The delay time is controlled by the delay time specifying signal of the delay time setting circuit (8).

Abstract translation: 用于均衡由薄膜磁头再现的信号的波形的电路，其消除波形的负边缘，而与头的特性的变化无关。 在均衡电路中，运算电路（7）接收包括负边缘的输入的读出信号并从薄膜磁头输出，并将所选择的磁头（1）的输入信号的波形在薄膜磁头 ，使用以下三个输出信号：输入端通过特性阻抗终止并且将输入信号延迟时间τ2的延迟电路（2,3）的输出，乘法电路（4）的输出用于 将延迟了时间（τ2-τ1）的信号乘以值K1和用于延迟输入信号的可变延迟时间电路（6）的输出，以便去除负沿。 均衡电路还设置有延迟设置电路（8），其根据表示头部（1）的位置和头部选择信号的信号来设置可变延迟时间电路（6）的延迟时间。 延迟时间由延迟时间设定电路（8）的延迟时间指定信号控制。

公开(公告)号：WO1993006593A1

公开(公告)日：1993-04-01

申请号：PCT/US1992007908

申请日：1992-09-24

Applicant: INTEGRAL PERIPHERALS, INC.

Inventor： INTEGRAL PERIPHERALS, INC. ,  COWEN, Stephen, R.

IPC: G11B05/09

CPC classification number: G11B5/09 ,  G11B5/59622 ,  G11B5/59655 ,  G11B19/00 ,  G11B19/12 ,  G11B19/28 ,  G11B20/10 ,  G11B20/1251 ,  G11B21/08 ,  G11B23/36 ,  G11B27/19 ,  G11B27/3027 ,  G11B2220/20 ,  G11B2220/2516

Abstract: The prerecorded embedded servo field (300) of this invention provides an enhanced level of functionality without increasing the servo field overhead. A prerecorded embedded servo field (300) includes a first sub-field (302) of prerecorded information that simultaneously provides (i) automatic gain control data for a third sub-field (306) and (ii) data for a first servo function, and a second sub-field (302) of prerecorded information that simultaneously provides (i) automatic gain control (AGC) data for the third sub-field (306) and (ii) data for a second servo function. Since the first and the second sub-fields (302, 303) in the servo field (300) of this invention are used for AGC and another servo function, the sub-fields are arranged within the servo field (300) so that the sub-field (302) that requires the least precise AGC control is first and the sub-field (306) that requires the most precise AGC control is last.

Abstract translation: 本发明的预先记录的嵌入式伺服字段（300）提供了增强的功能级别，而不增加伺服字段开销。 预先记录的嵌入式伺服字段（300）包括预先记录的信息的第一子字段（302），其同时提供（i）用于第三子场（306）的自动增益控制数据和（ii）用于第一伺服功能的数据， 以及同步提供（i）用于第三子场（306）的自动增益控制（AGC）数据和（ii）用于第二伺服功能的数据的预先记录信息的第二子场（302）。 由于本发明的伺服字段（300）中的第一和第二子场（302,303）用于AGC和另一个伺服功能，所以子场被布置在伺服字段（300）内，使得子 首先需要最不精确的AGC控制的场（302），并且需要最精确的AGC控制的子场（306）是最后的。

公开(公告)号：WO1992009074A1

公开(公告)日：1992-05-29

申请号：PCT/US1991008459

申请日：1991-11-13

Applicant: WANGTEK, INC.

Inventor： WANGTEK, INC. ,  VUONG, Binh

IPC: G11B05/09

CPC classification number: G06F3/0601 ,  G06F2003/0698 ,  G11B20/10 ,  G11B20/10527 ,  G11B2020/10814

Abstract: A system and method for slowing the data transfer rate in a magnetic tape cartridge drive is presented for a better match in transfer rates between a host computer and the drive. The transfer is slowed after the start of the data transfer operation to selected transfer rates (64, 90) below the nominal transfer rate fo the drive. The requirement of density of data on the magnetic tape remains unaffected so that the magnetic tapes are interchangeable with present drives.

Abstract translation: 提出了一种用于在磁带驱动器中减慢数据传输速率的系统和方法，以便在主计算机和驱动器之间的传输速率更好地匹配。 在数据传输操作开始之后传输速度降低到低于驱动器标称传输速率的选定传输速率（64,90）。 对磁带上的数据密度的要求保持不受影响，使得磁带可与当前驱动器互换。

公开(公告)号：WO1992002928A1

公开(公告)日：1992-02-20

申请号：PCT/US1991004515

申请日：1991-06-24

Applicant: CONNER PERIPHERALS, INC.

Inventor： CONNER PERIPHERALS, INC. ,  SHRINKLE, Louis, J.

IPC: G11B05/09

CPC classification number: G11B20/10212 ,  G11B5/09

Abstract: A microcontroller managed adaptive control system, including a precompensator (76) and a passive equalizer, is provided to decrease the read error rate of a disk drive. An adaptively controllable programmable precompensator adjusts the timing of data bits (84) being written to disk recording surface with the timing adjustement being relative to the individual bit timing windows. A novel adaptively controllable programmable equalization circuit (78) is provided to enhance the peak amplitudes of data bits read high frequencies. A microcontroller is programmed to control the programmable precompensator and equalizer to determine the threshold for and subsequently enable the precompensation of the write data and, independently, the equalization of read data with respect to a given media surface.

Abstract translation: 提供微控制器管理的自适应控制系统，包括预补偿器（76）和无源均衡器，以减小磁盘驱动器的读错误率。 自适应控制的可编程预补偿器调整被写入盘记录表面的数据位（84）的定时，其中定时调整是相对于各个位定时窗口。 提供了一种新颖的可自适应控制的可编程均衡电路（78），以增强读高频数据位的峰值幅度。 微控制器被编程为控制可编程预补偿器和均衡器以确定写入数据的预补偿并且随后使能读取数据相对于给定介质表面的均衡。

公开(公告)号：WO1991006094A1

公开(公告)日：1991-05-02

申请号：PCT/US1990004765

申请日：1990-08-22

Applicant: CONNER PERIPHERALS, INC.

Inventor： CONNER PERIPHERALS, INC. ,  SQUIRES, John, P. ,  SHRINKLE, Louis, J.

IPC: G11B05/09

CPC classification number: G11B20/10009 ,  G11B20/1816

Abstract: The read/write channel is programmatically adaptable to the media use for storing data in response to data signals and the read/write head used to transfer the data signals to and from the media. Adaptability is provided by programmable signal processing elements in the read/write channel. The programmable elements include a read threshold element (THR) for determining whether data signals transferred from the media exceed a data discrimination level determined by a first programmable value (TH0-2), and a data window element (WND) for determining whether data signals transferred from the media occur within a data signal window whose timing, relative to a data clock signal, is determined by the second programmable value (W0-2). Additional programmable elements include an amplifier element that is programmed to provide a corresponding level of write current and a precompensation block for providing data signal precompensation. The programmable values are determined by the disk drive uniquely for the media, read/write head and the read/write data channel.

Abstract translation: 读/写通道以编程方式适用于响应于数据信号存储数据的媒体使用以及用于将数据信号传送到媒体和从媒体传送数据信号的读/写头。 适应性由读/写通道中的可编程信号处理元件提供。 可编程元件包括用于确定从介质传送的数据信号是否超过由第一可编程值（TH0-2）确定的数据鉴别级别的读阈值元件（THR），以及用于确定数据信号 从媒体发送的数据信号窗口中，相对于数据时钟信号的定时由第二可编程值（W0-2）确定。 附加的可编程元件包括被编程为提供相应级别的写入电流的放大器元件和用于提供数据信号预补偿的预补偿块。 可编程值由介质，读/写头和读/写数据通道唯一的磁盘驱动器确定。

公开(公告)号：WO1990009021A1

公开(公告)日：1990-08-09

申请号：PCT/US1990000529

申请日：1990-01-23

Applicant: MAXTOR CORPORATION

Inventor： MAXTOR CORPORATION ,  HUBER, William, D.

IPC: G11B05/09

CPC classification number: G11B20/10046 ,  G11B20/10009

Abstract: A read channel detector circuit for recovery of digital data from a readback waveform produced by a magnetic recording head is disclosed. The detector circuit includes a forward filter (20) for slimming the rising edge and slurring the falling edge of an isolated input magnetic pulse. Quantized feedback techniques (23) are then used to produce a compensating waveform (O) which is substantially complementary to the slurred falling edge of the isolated magnetic pulse (8). The complementary waveform is added (21) to the forward filter output to produce a waveform (E) which is substantially a step function. This step function corresponds to a single digital transition, either positive-going or negative-going in a digital output sequence. The equalized waveform is then limited by a comparator (22) to produce the desired digital output sequence. By slimming only the rising edge of the input magnetic pulse and by using quantized feedback techniques, the overall bandwidth of the system is conserved resulting in an increased binary signalling capability without substantial intersymbol interference.

公开(公告)号：WO1988009031A1

公开(公告)日：1988-11-17

申请号：PCT/US1988001442

申请日：1988-05-09

Applicant: EXABYTE CORPORATION

Inventor： EXABYTE CORPORATION ,  HINZ, Harry, C. ,  ZOOK, Christopher, P.

IPC: G11B05/09

CPC classification number: G11B5/0086 ,  G11B20/1209

Abstract: Apparatus and method are disclosed for formatting and recording digital information. Recording is effected by discrete stripes on 8 mm magnetic tape using a helical scan arrangement that enables a high recording density and a low error rate. Formatting in the data area of each stripe includes recording of digital information with preamble, data block, and postamble sections. The preamble section provides frequency/phase (98) and location referencing (100), the data block section includes a plurality of physical data blocks each of which are divided into sub-blocks that include synchronizing and identifying information along with data to be recorded, and the postamble section ensures compatibility of physical alignement between the recording heads and magnetic tape.

公开(公告)号：WO1988005954A1

公开(公告)日：1988-08-11

申请号：PCT/US1988000307

申请日：1988-02-03

Applicant: MAXTOR CORPORATION

Inventor： MAXTOR CORPORATION ,  HUBER, Don

IPC: G11B05/09

CPC classification number: G11B20/10046 ,  G11B20/10009

Abstract: A channel filter employing time domain targeting techniques to eliminate inter symbol interference in the reading of information from magnetic media. A pulse detector (16) outputs a signal characteristic of polarity reversals on the surface of magnetic storage media. This output signal is coupled to a tapped delay line network (17) and a moderate order L-C network (27). The tapped delay line provides an output signal to the L-C network, which flattens out pre-cursive and post-cursive undershoots. As a result, a moderate order L-C network is sufficient to approximate the desired target response so that maximum information density can be achieved. The tapped delay line provides an output signal (57, 58) that consists of a superposition (sum) of the input signal delayed and weighted. This forms a transversal filter. As with any linear filter, reciprocity applies. Consequently, the output of the tapped delay line is taken from the input with AC coupling directly to ground. The output is taken from a low characteristic impedance, eliminating the need for an internal amplifier capable of driving a low impedance equal to the characteristic impedance of the delay line.

公开(公告)号：WO1985000067A1

公开(公告)日：1985-01-03

申请号：PCT/JP1984000312

申请日：1984-06-15

Applicant: SONY CORPORATION ,  TANAKA, Masato ,  HIMENO, Takuji

Inventor： SONY CORPORATION

IPC: G11B05/09

CPC classification number: H03M5/14 ,  G11B20/1423 ,  Y10T82/10 ,  Y10T82/13 ,  Y10T82/2502

Abstract: In a method of modulating a data bit series consisting of a first value (e.g., 1) and a second value (e.g., 0), inversion is used as a condition transition so that the following conditions (a) to (d) are satisfied: (a) inversion occurs at the boundary between bit cells sandwiched between "0" bits; (b) inversion occurs at the center of a bit cell containing a "1" bit; (c) inversion is prevented at the center of each of the last two bit cells containing "1" bits of an even number of bit cells containing "1" bits sandwiched between "0" bits, but inversion occurs at the boundary between these last two bit cells containing "1" bits; and (d) when at least one pattern of which the two bits are "0" and "1" occurs next to an even number of "1" bits after a "0" bit, inversion occurs at the center of the bit cell containing the "0" bit of the first two bits.