METODO Y APARATO PARA REGISTRAR UNA SEÑAL BINARIA SOBRE UN PORTADOR DE REGISTRO.

    公开(公告)号:MX9705107A

    公开(公告)日:1997-10-31

    申请号:MX9705107

    申请日:1996-10-30

    Abstract: Se descubre un método y un aparato para registrar una señal binaria sobre un portador (45) magnético de registro. La señal binaria es abastecida a una terminal (30) de entrada. El aparato consta de los generadores (38.1 a 38.4) para generar por lo menos dos impulsos (P1, P2) de escritura para cada bit de la señal binaria que va a ser escrito. Más específicamente, los generadores está adaptados para (i) generar por lo menos dos impulsos de escritura de una tercera polaridad (P1, P2) para el primer bit de la primera polaridad en la primera secuencia, (ii) generar un impulso de escritura de la tercera polaridad y un impulso de escritura de una cuarta polaridad (P3, P4) para por lo menos el segundo bit de la primera polaridad que acontece en la primera secuencia; la tercera polaridad es opuesta a la cuarta polaridad, (iii) generar por lo menos dos impulsos de escritura de la cuarta polaridad (P7, P8) para el primer bit de la segunda polaridad en la segunda secuencia (iv) generar un impulso de escritura de la tercera polaridad y un impulso de escritura de la cuarta polaridad (P3', P4') para, por lo menos, el segundo bit de la segunda polaridad que acontece en la segunda secuencia.

    SISTEMA DE RASTREO Y SEGURIDAD DE MEDIOS DE VIDEO.

    公开(公告)号:MX9708326A

    公开(公告)日:1998-01-31

    申请号:MX9708326

    申请日:1996-05-13

    Abstract: Un sistema para proporcionar datos de rastreo y seguridad para medios de video de renta, entre los que se incluyen discos digitales de video y casetes digitales de video. Los nuevos formatos de las reproductoras de video y medios permiten la inclusion de características de seguridad que permiten el rastreo de la renta de esos medios y, a la vez, evitan la renta no autorizada de los mismos. Cada reproductora incluye un circuito de decision que reproduce un disco particular ( o cinta) solamente si el numero de identificacion de la reproductora, que está grabado en una tarjeta de memoria de autorizacion, separada, especial, es idéntico al numero de identificacion de la reproductora grabado en la misma, y si un numero de identificacion de película que se lee opticamente a partir del disco coincide con el numero de identificacion de película grabado en la tarjeta especial. Se proporciona un aparato correspondiente en el establecimiento de renta de video con el que, al momento de rentar el video, se graba en la tarjeta de autorizacion, en forma cifrada, el numero de identificacion y el numero de la reproductora de discos en particular para la cual está destinada la renta. El cifrado utiliza una clave especial de un sistema publico de claves, la clave publica y el modulo se graban previamente en la porcion optica del disco.

    Volume recovery system for data sets in a word processing system
    3.
    发明公开
    Volume recovery system for data sets in a word processing system 失效
    用于数据集的音量恢复系统在字处理系统中

    公开(公告)号:EP0118954A3

    公开(公告)日:1988-06-22

    申请号:EP84200318

    申请日:1984-03-06

    CPC classification number: G06F17/30955 G06F3/0601 G06F2003/0697

    Abstract: In a word processing system 10 storing a text stream on a direct access storage device (DASD) for recall and editing, the text stream is organized into a document, which is stored on the DASD 22 as a data set. The data setconsists of an index portion and a portion containing text records. The index portion is divided into nodes, of which the primary node is called the root node. A volume 500 which refers to the full contents of the DASD can be formatted to contain multiple zones 502-508, each of which is logically independent of all other zones, when the contents of a storage volume can be divided conceptually into portions the uses of which are logically independent. Each zone has its own media allocation map, and data sets 510-522 whose root is allocated within a given zone have all allocations within that same zone. If more than one data set with a given data set type exists on the storage volume, all of those data sets 511, 513, 516 and the data set directory 520 for that data set type are allocated within a single zone 504. For each zone, a recovery required indicator 325 is provided so that zones not requiring recovery need not be scanned when volume recovery is being performed. When only one zone is being recoverd, the logical sector number of the root node referenced by the index element in the anchor is used to determine whether or not that data set lies in the zone being recovered, and to skip data sets that do not lie in the zone (675-691).

    Address indication circuit capable of relatively shifting channel addresses relative to memory addresses
    4.
    发明公开
    Address indication circuit capable of relatively shifting channel addresses relative to memory addresses 失效
    相对于存储器地址的相对移位通道地址指示电路

    公开(公告)号:EP0123322A3

    公开(公告)日:1987-09-09

    申请号:EP84104700

    申请日:1984-04-26

    CPC classification number: G11B20/1809 G11B20/12

    Abstract: in an address indication circuit for use in indicating memory addresses of a random access memory to provide delays necessary for successive channels, channel addresses are determined relative to the memory addresses by assigning a reference number to a leading one of the channels and by successively accumulating the reference number and numbers determined for the delays to decide results of accumulation as the remaining channel addresses. The respective channel addresses are stored in a read-only memory (80) and added by an adder (83) to a base address variable at every time interval to provide memory addresses. When the memory addresses are equal in number to a preselected number, the base address may be produced by a counter (81) carrying out operation between zero and the preselected number less one. The adder adds the reference number to the base address modulo the preselected number.

    On-the-fly multibyte error correction
    5.
    发明公开
    On-the-fly multibyte error correction 失效
    多功能多功能错误校正

    公开(公告)号:EP0114938A3

    公开(公告)日:1987-02-25

    申请号:EP83110505

    申请日:1983-10-21

    CPC classification number: H03M13/151 G11B5/09 H03M13/1545 H03M13/1585

    Abstract: In the multibyte error correcting system, up to t errors are correctable by processing 2t syndrome bytes. Syndrome bytes are converted into t+1 coefficients of the error locator polynomial by predetermined product operations and exclusive-OR operations involving selected syndrome bytes to produce cofactors that correspond to the desired coefficients when less then t errors occurred in the codeword. The cofactors are combined to produce coefficients when t errors occur and the correct set of coefficients are selected in accordance with the number of errors that are detected. Up to t erroneous bytes in one codeword and corrected during its transfer from the system while the next codeword is entered in the system, so that correction is on-the-fly.

    Apparatus for decoding video address code signals
    6.
    发明公开
    Apparatus for decoding video address code signals 失效
    解码视频地址码信号的装置

    公开(公告)号:EP0109551A3

    公开(公告)日:1986-12-03

    申请号:EP83110417

    申请日:1983-10-19

    Inventor: Moxon, Edwin C.

    CPC classification number: G11B20/1813 G11B27/3054 G11B2220/90

    Abstract: Apparatus for decoding digitally-coded address signals embedded in video signals recorded on magnetic tape is disclosed. The apparatus can properly decode the address signals at both slow and fast tape speeds and utilizes a variable-frequency oscillator to generate timing signals for decoding the digitally-coded address. The address signals encoded on the magnetic tape normally include an error code which can be detected by conventional error checking circuitry and used to check whether the address signals have been correctly received. The oscillator frequency is adjusted in accordance with an error signal generated by the error checking circuitry until error-free detection of the address signals is achieved.

    Error correction method and system
    7.
    发明公开
    Error correction method and system 失效
    错误校正方法和系统

    公开(公告)号:EP0129849A3

    公开(公告)日:1986-04-09

    申请号:EP84107110

    申请日:1984-06-20

    Applicant: HITACHI, LTD.

    CPC classification number: G11B20/1809

    Abstract: This invention relates to an error correction upon reproduction of digital signals. The error correction is performed by decoding code words such as cross-interleaved Reed Solomon codes, in which first code blocks are formed by a plurality of information words which are in the first arrangement state and a plurality of first check words which are produced by codes associated with the plurality of information words with a Hamming distance of d,, and second code blocks are formed by a plurality of information words and a plurality of first check words which are in the second arrangement state and which consist of the said plurality of information words and the said plurality of first check words which are respectively included in the different first code blocks, and by a plurality of second check words which are produced by codes associated with the plurality of information words and the plurality of first check words with a Hamming distance of d 2 . At the first decoding stage, at least errors are detected and at the same time the flags indicative of the decoding states are i added with respect to the second code blocks. At the second decoding stage, in accordance with the contents of the flags and on the basis of a combination of p 2 and q selected from their combinations satisfying 2p 2 +q≤d 1 -1, errors are detected and errors of p 2 words are corrected and erasures of q words to which the flags were added are corrected with respect to the first code blocks.

    An arrangement for encoding and decoding information signals
    8.
    发明公开
    An arrangement for encoding and decoding information signals 失效
    编码和解码信息信号的安排

    公开(公告)号:EP0094293A3

    公开(公告)日:1985-09-18

    申请号:EP83400869

    申请日:1983-04-29

    CPC classification number: G11B20/1426

    Abstract: The present invention provides translation circuitry, which in one mode of operation acts to encode variable length data words into fixed rate data coded words for use with a communication channel, or a recording means, such as a magnetic recording medium and which in another mode of operation acts to decode the coded words to data words. The translation circuitry functions such that in an encoding operation, the second and third bits of a three-bit coded word, respectively, have the same binary values as the first and second bits of the data word, which the coded word represents and the second and sixth bits of a six-bit coded word, respectively, have the same binary values as the third and fourth bits of the data word which the coded word represents.

    Time base correcting apparatus
    9.
    发明公开
    Time base correcting apparatus 失效
    时基校正装置

    公开(公告)号:EP0086658A3

    公开(公告)日:1984-07-25

    申请号:EP83300741

    申请日:1983-02-15

    Abstract: A time base correcting apparatus is capable of correcting time base erros contained in a digital signal supplied thereto in the form of successive data blocks each data block including a plurality of data words and a block address which cycles with a predetermined phase relation relative to a certain reference signal. A memory (16) is provided, having a plurality of addressable storage locations, each arranged to store a respective data block. A write-in address (21) to identify the particular storage locations is generated according to data block addresses and read-out addresses. The write-in address (21) is varied (29) by a lock phase mode signal (5) indicative of a phase relation at which an incoming digital signal is locked to a reference signal, so that notwithstanding the phase mode in which the digital signal is locked to the reference signal, the correction ability of the time base correcting apparatus can be prevented from being lowered.

    Pulse code modulated signal processing apparatus
    10.
    发明公开
    Pulse code modulated signal processing apparatus 失效
    脉冲码调制信号处理装置

    公开(公告)号:EP0053505A3

    公开(公告)日:1983-07-06

    申请号:EP81305641

    申请日:1981-11-27

    CPC classification number: G11B20/1809

    Abstract: A PCM signal processing apparatus is arranged to receive successive transmission blocks, each of which comprise time-interleaved PCM data, error correction and error detection words. The apparatus has an error detector (16) responsive to the error detection words for detecting errors in a received transmission block and error identifying means (18, 22, 23) for identifying errors in each of the time-interleaved words included in the received transmission block which has been detected. A de-interleaver (17) is provided for time-deinterleaving each received transmission block to recover a de-interleaved block comprising de-interleaved PCM and error correction words, with errors in the de-interleaved words being respectively identified. A syndrome generating device (18) is coupled to the de-interleaver (17) for generating error syndromes using the de-interleaved PCM and error correction words in the de-interleaved block. An error correcting device (20) responsive to the error syndromes corrects erroneous PCM words in the de-interleaved block as a function of the remaining error free PCM and the error correction words in the de-interleaved block. An error compensating device (21) is responsive to the identification of errors by the error identifying device and compensates the erroneous PCM words in the de-interleaved block with a substitute PCM word when error correction by the error correcting device (20) is impossible. An inhibit device (24) inhibits the error correcting device (20) when all of the error detection words in the de-interleaved block are identified as erroneous and it discontinues inhibiting when the relationship between the identification by the error identifying device and the error syndrome indicates that no error exists.

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