公开(公告)号：US20240304224A1

公开(公告)日：2024-09-12

申请号：US18583568

申请日：2024-02-21

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Christophe GONCALVES ,  Marc BATTISTA ,  Francois TAILLIET

IPC: G11C7/08 ,  G11C7/10

CPC classification number: G11C7/08 ,  G11C7/1048 ,  G11C7/1069

Abstract: The present disclosure relates to a method of reading a word in a memory device, wherein the word is comprised in a first set of words that can be read by the memory device, each word of the first set comprising at least one byte of data, each word being contained in memory cells, the method comprising a pre-charging step during which the first set and at least a second set of words are pre-charged, a first terminal of each cell of the first and second sets being floating during the pre-charging step.

公开(公告)号：US12088326B2

公开(公告)日：2024-09-10

申请号：US17940236

申请日：2022-09-08

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Abhishek Jain

IPC: H03M3/00 ,  H03K3/356 ,  H03M1/06

CPC classification number: H03M3/464 ,  H03K3/356 ,  H03M1/0626 ,  H03M3/43

Abstract: A continuous time, sigma-delta analog-to-digital converter circuit includes a sigma-delta modulator circuit configured to receive an analog input signal. A single bit quantizer of the modulator generates a digital output signal at a sampling frequency. A data storage circuit stores bits of the digital output signal and digital-to-analog converter (DAC) elements are actuated in response to the stored bits to generate an analog feedback signal for comparison to the analog input signal. A filter circuit includes polyphase signal processing paths and a summation circuit configured to sum outputs from the polyphase signal processing paths to generate a converted output signal. A fan out circuit selectively applies the stored bits from the data storage circuit to inputs of the polyphase signal processing paths of the filter circuit.

公开(公告)号：US12088085B2

公开(公告)日：2024-09-10

申请号：US18157737

申请日：2023-01-20

Applicant: STMICROELECTRONICS (ROUSSET) SAS ,  STMicroelectronics International N.V.

Inventor： Manoj Kumar ,  Ravinder Kumar ,  Nicolas Demange

IPC: H02H3/20 ,  H02H1/00

CPC classification number: H02H3/20 ,  H02H1/0007

Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.

公开(公告)号：US20240297044A1

公开(公告)日：2024-09-05

申请号：US18583752

申请日：2024-02-21

Applicant: STMicroelectronics International N.V.

Inventor： Cateno Marco CAMALLERI ,  Mario Giuseppe SAGGIO ,  Edoardo ZANETTI ,  Gabriele BELLOCCHI

IPC: H01L21/04

CPC classification number: H01L21/0465

Abstract: A manufacturing process provides for: forming a semiconductor body of silicon carbide, having a front surface; performing a localized ion implantation to form implanted regions in implant portions in the semiconductor body. The step of performing a localized ion implantation provides for: forming damaged regions at the front surface, separated from each other by the implant portions in a direction parallel to the front surface; performing a channeled ion implantation, for implanting doping ions within the semiconductor body and forming the implanted regions at the implant portions of the semiconductor body. The channeled ion implantation is performed in a self-aligned manner with respect to the damaged regions, which represent damaged regions of the silicon-carbide crystallographic lattice such as to block a propagation of the channeled ion implantation along a vertical axis orthogonal to the front surface, in a depth direction of the semiconductor body.

公开(公告)号：US20240292610A1

公开(公告)日：2024-08-29

申请号：US18586440

申请日：2024-02-24

Applicant: STMicroelectronics International N.V.

Inventor： Pascal FORNARA

IPC: H10B20/25 ,  G11C17/06 ,  G11C17/18 ,  H10B99/00

CPC classification number: H10B20/25 ,  G11C17/06 ,  G11C17/18 ,  H10B99/16

Abstract: A memory cell is formed by a PIN diode having three contacts. A breakdown voltage is applied to break down a gate oxide arranged between a region of the PIN diode and a substrate region. The breakdown or non-breakdown state of the gate oxide is determined by applying a read voltage between the anode and the cathode of the diode and determining the value of the corresponding current flowing in the diode.

公开(公告)号：US20240291488A1

公开(公告)日：2024-08-29

申请号：US18582446

申请日：2024-02-20

Applicant: STMicroelectronics International N.V.

Inventor： Ravinder KUMAR ,  Saiyid Mohammad Irshad RIZVI

IPC: H03K19/003 ,  H03K19/0175

CPC classification number: H03K19/00369 ,  H03K19/017545 ,  H03K19/017581

Abstract: The present disclosure is directed to a voltage driver, where a combination of first and second resistance blocks controls a differential voltage swing on the outputs of the voltage driver. Variations of an input voltage are compensated by adding different values of the first resistance block to the second resistance block, while keeping a summation of the first and second resistance blocks at a constant value. Three different circuit diagrams are disclosed to generate these different resistances. In each circuit diagram, one or more control signals change the resistance of the combination of first and second resistance blocks. In some embodiments, the value of the second resistance block is changed by the first resistance block to maintain an impedance matching between a transmitter and a receiver, while changing of the first resistance block compensates for the differential voltage swing.

公开(公告)号：US20240288557A1

公开(公告)日：2024-08-29

申请号：US18176163

申请日：2023-02-28

Applicant: STMicroelectronics International N.V.

Inventor： Stuart McLeod ,  Andreas Assmann

IPC: G01S7/4865 ,  G01S7/48 ,  G01S17/89

CPC classification number: G01S7/4865 ,  G01S7/4808 ,  G01S17/89

Abstract: A method of determining a distance of a closest target using a time-of-flight (ToF) ranging system includes: receiving, by a processor, a histogram generated by a ToF imager of the ToF ranging system, where the ToF imager is configured to transmit a light pulse for ranging purpose; finding a first rising edge in the histogram that corresponds to a rising edge of a reflected light pulse from the closest target; and calculating a first estimate of the distance of the closest target by adding a pre-determined offset to a distance of the first rising edge.

公开(公告)号：US12073308B2

公开(公告)日：2024-08-27

申请号：US15423279

申请日：2017-02-02

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Thomas Boesch ,  Giuseppe Desoli

IPC: G06N3/063 ,  G06F30/327 ,  G06F30/34 ,  G06F30/347 ,  G06N3/044 ,  G06N3/045 ,  G06N3/0464 ,  G06N3/047 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06F9/445 ,  G06F13/40 ,  G06F15/78 ,  G06F115/02 ,  G06F115/08 ,  G06N3/04 ,  G06N3/08 ,  G06N7/01

CPC classification number: G06N3/0464 ,  G06F30/327 ,  G06F30/34 ,  G06F30/347 ,  G06N3/044 ,  G06N3/045 ,  G06N3/047 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06F9/44505 ,  G06F13/4022 ,  G06F15/7817 ,  G06F2115/02 ,  G06F2115/08 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N7/01

Abstract: Embodiments are directed towards a hardware accelerator engine that supports efficient mapping of convolutional stages of deep neural network algorithms. The hardware accelerator engine includes a plurality of convolution accelerators, and each one of the plurality of convolution accelerators includes a kernel buffer, a feature line buffer, and a plurality of multiply-accumulate (MAC) units. The MAC units are arranged to multiply and accumulate data received from both the kernel buffer and the feature line buffer. The hardware accelerator engine also includes at least one input bus coupled to an output bus port of a stream switch, at least one output bus coupled to an input bus port of the stream switch, or at least one input bus and at least one output bus hard wired to respective output bus and input bus ports of the stream switch.

公开(公告)号：US12068057B2

公开(公告)日：2024-08-20

申请号：US18056803

申请日：2022-11-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V. ,  STMicroelectronics Application GMBH

Inventor： Asif Rashid Zargar ,  Nicolas Bernard Grossier ,  Charul Jain ,  Roberto Colombo

IPC: G11C7/24 ,  G11C7/10

CPC classification number: G11C7/24 ,  G11C7/1039 ,  G11C7/1069

Abstract: In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.

公开(公告)号：US12068048B2

公开(公告)日：2024-08-20

申请号：US17815807

申请日：2022-07-28

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics International N.V.

Inventor： Vivek Mohan Sharma ,  Roberto Colombo

IPC: G11C29/24 ,  G11C29/36 ,  G11C29/42 ,  G11C29/48

CPC classification number: G11C29/42 ,  G11C29/36 ,  G11C29/48 ,  G11C2029/3602

Abstract: A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.