公开(公告)号：WO2006129194A2

公开(公告)日：2006-12-07

申请号：PCT/IB2006/001702

申请日：2006-05-26

Applicant: ATI TECHNOLOGIES, INC. ,  ATI INTERNATIONAL SRL ,  KELLY, Tim ,  KADURI, Raja ,  BEHR, Dominik

Inventor： KELLY, Tim ,  KADURI, Raja ,  BEHR, Dominik

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06F9/52 ,  G06T1/20 ,  G06T2210/52

Abstract: A system and method for frame synchronization in multiple video processing unit (VPU) systems is described. In various embodiments, multiple VPUs cooperatively process frame data for display. According to embodiments, more than one VPU may not reside on a same card such that conventional synchronization methods are available. Frame data synchronization is accomplished in various embodiments by using semaphore mechanisms and by writing values to shared memory locations. For synchronization of execution among multiple VPUs operating on a same command buffer, execution of commands by one or more VPUs is stalled based on a semaphore value or a value in a shared memory location.

Abstract translation: 描述了用于多视频处理单元（VPU）系统中的帧同步的系统和方法。 在各种实施例中，多个VPU协同处理帧数据以进行显示。 根据实施例，多于一个VPU可能不驻留在同一卡上，使得传统的同步方法是可用的。 帧数据同步在各种实施例中通过使用信号量机制和将值写入共享存储器位置来实现。 为了在同一命令缓冲器上操作的多个VPU之间的执行同步，一个或多个VPU的命令的执行基于信号量值或共享存储器位置中的值而停止。

公开(公告)号：WO2006126090A2

公开(公告)日：2006-11-30

申请号：PCT/IB2006/001463

申请日：2006-05-26

Applicant: ATI TECHNOLOGIES INC. ,  ATI INTERNATIONAL SRL ,  KELLY, Tim ,  CAMPBELL, Jon ,  GOTWALT, David

Inventor： KELLY, Tim ,  CAMPBELL, Jon ,  GOTWALT, David

IPC: G06F15/80

CPC classification number: G06F9/30069 ,  G06F9/30072 ,  G06F9/3885

Abstract: A system and method for applying non-homogeneous properties to multiple video processing units (VPUs) in a multiple VPU system are described. Respective VPUs in the system cooperate to produce a frame to be displayed. In various embodiments, data output by different VPUs in the system is combined, or merged, or composited to produce a frame to be displayed. In load balancing modes, each VPU in the system performs different tasks as part of rendering a same frame, and therefore typically executes different commands. In various embodiments, efficiency of the system is enhanced by forming a single command buffer for execution by all of the VPUs in the system even though each VPU may have a different set of commands to execute in the command buffer.

Abstract translation: 描述了将多个VPU系统中的多个视频处理单元（VPU）应用非均匀特性的系统和方法。 系统中的相应VPU协同生成要显示的帧。 在各种实施例中，由系统中的不同VPU输出的数据被组合，合并或合成以产生要显示的帧。 在负载平衡模式下，系统中的每个VPU执行不同的任务作为渲染相同帧的一部分，因此通常执行不同的命令。 在各种实施例中，即使每个VPU可以具有在命令缓冲器中执行的不同命令集，通过形成用于系统中的所有VPU执行的单个命令缓冲器来增强系统的效率。

公开(公告)号：WO2006106428A2

公开(公告)日：2006-10-12

申请号：PCT/IB2006/000973

申请日：2006-04-06

Applicant: ATI TECHNOLOGIES, INC ,  ATI INTERNATIONAL SRL ,  KRUGER, W., Fritz ,  DREBIN, Robert, A. ,  SMITH, Wade, K.

Inventor： KRUGER, W., Fritz ,  DREBIN, Robert, A. ,  SMITH, Wade, K.

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F2212/652

Abstract: A method and apparatus for fragment processing in a virtual memory system are described. Embodiments of the invention include a coprocessor comprising a virtual memory system for accessing a physical memory. Page table logic and fragment processing logic scan a page table having a fixed, relatively small page size. The page table is broken into fragments made up of pages that are contiguous in physical address space and logical address space and have similar attributes. Fragments in logical address space begin on known boundaries such that the boundary indicates both a starting address of a fragment and the size of the fragment. Corresponding fragments in physical address space can begin anywhere, thus making the process transparent to physical memory. A fragment field in a page table entry conveys both fragment size and boundary information.

Abstract translation: 描述了虚拟存储器系统中的片段处理的方法和装置。 本发明的实施例包括协处理器，其包括用于访问物理存储器的虚拟存储器系统。 页表逻辑和片段处理逻辑扫描具有固定的相对小的页面大小的页表。 页表被分解成由物理地址空间和逻辑地址空间中连续的页构成的，具有相似属性的片段。 逻辑地址空间中的片段从已知边界开始，使得边界指示片段的起始地址和片段的大小。 物理地址空间中的相应片段可以从任何地方开始，从而使处理对物理内存透明。 页表条目中的片段字段传达片段大小和边界信息。

公开(公告)号：WO2006100593A1

公开(公告)日：2006-09-28

申请号：PCT/IB2006/000700

申请日：2006-03-24

Applicant: ATI TECHNOLOGIES, INC ,  ATI INTERNATIONAL SRL ,  ALEKSIE, Milivoje ,  MUNSHI, Aaftab ,  OGDEN, Charles, D.

Inventor： ALEKSIE, Milivoje ,  MUNSHI, Aaftab ,  OGDEN, Charles, D.

IPC: G06T9/00

CPC classification number: H04N19/94 ,  H04N19/124 ,  H04N19/186 ,  H04N19/42 ,  H04N19/426

Abstract: A block-based image compression method and encoder/decoder circuit compresses a plurality of pixels having corresponding original color values and luminance values in a block according to different modes of operation. The encoding circuit includes a luminance-level- based representative color generator to generate representative color values for each of a plurality of luminance levels derived from the corresponding luminance levels to produce at least a block color offset value and a quantization value. According to mode zero, each of the pixels in the block is associated with one of the plurality of generated representative color values to generate error map values and a mode zero color error value. According to mode one, representative color values for each of at least three luminance levels are also generated to produce at least three representative color values, corresponding bitmap values and a mode one color error value. A mode based compressed data generator is capable of operating in mode zero and/or one and produces block color mode zero data when the mode zero color error value is less than the mode one color error value, otherwise block color mode one data.

Abstract translation: 基于块的图像压缩方法和编码器/解码器电路根据不同的操作模式来压缩具有对应的原始颜色值和亮度值的多个像素。 编码电路包括基于亮度级的代表颜色发生器，用于针对从相应的亮度级别导出的多个亮度级中的每一个产生代表色彩值，以产生至少块色偏移值和量化值。 根据模式零，块中的每个像素与多个生成的代表色彩值中的一个相关联，以产生误差图值和模式零色误差值。 根据模式1，还生成至少三个亮度级中的每一个的代表性颜色值，以产生至少三个代表性颜色值，对应的位图值和模式一个颜色误差值。 当模式零颜色误差值小于模式一个颜色误差值时，基于模式的压缩数据生成器能够以模式零和/或一个运行，并产生块颜色模式零数据，否则块颜色模式一个数据。

公开(公告)号：WO2006053321A9

公开(公告)日：2006-07-27

申请号：PCT/US2005041325

申请日：2005-11-14

Applicant: ATI TECHNOLOGIES INC ,  BROWN ANDREW S

Inventor： BROWN ANDREW S

IPC: G06F1/04

CPC classification number: G06F1/04 ,  G06F1/08 ,  G11C17/143 ,  G11C17/165 ,  G11C17/18 ,  G11C29/785 ,  G11C2029/4402

Abstract: Systems and methods for controlling clock rates of circuits are provided. The systems and methods, collectively referred to as clock rate control, generate a clock rate control parameter from data of one or more fuses. The clock rate control detects any overclocked signal of received clock signals by determining a clock signal is running faster than a threshold represented by the clock rate control parameter. The clock rate control controls a circuit clock rate using a selected signal of the clock signals that is not an overclocked signal.

Abstract translation: 提供了控制电路时钟速率的系统和方法。 统称为时钟速率控制的系统和方法根据一个或多个保险丝的数据生成时钟速率控制参数。 时钟速率控制通过确定时钟信号的运行速度高于由时钟速率控制参数表示的阈值来检测接收的时钟信号的任何超频信号。 时钟速率控制使用不是超频信号的时钟信号的选定信号来控制电路时钟速率。

公开(公告)号：WO2006075250A2

公开(公告)日：2006-07-20

申请号：PCT/IB2006000173

申请日：2006-01-13

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  ORR STEPHEN J

Inventor： ORR STEPHEN J

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/325 ,  Y02D50/20

Abstract: Method and apparatus for controlling power consumption of a plug-in card or circuit module (104). Power to a circuit module (104) is controlled by a user interface (116) and power manager (114) to automatically control the power state of the circuit module (104) by, among other things, powering the module up or down using a simulated hot unplug of the module (104). The apparatus further includes use of an I/O interconnect (126) to allow the system BIOS (122) to simulate the hot unplugging of the module (104).

Abstract translation: 用于控制插入式卡或电路模块（104）的功率消耗的方法和装置。 电路模块（104）的电源由用户接口（116）和电源管理器（114）控制，以通过使用电源模块（104）向上或向下供电来自动控制电路模块 模拟热拔掉模块（104）。 该装置还包括使用I / O互连（126）以允许系统BIOS（122）模拟模块（104）的热拔出。

公开(公告)号：WO2006030317A3

公开(公告)日：2006-03-23

申请号：PCT/IB2005/003086

申请日：2005-09-16

Applicant: ATI TECHNOLOGIES, INC. ,  ATI INTERNATIONAL SRL ,  AZENKOT, Yehuda ,  RAKIB, Selim, Shlomo

Inventor： AZENKOT, Yehuda ,  RAKIB, Selim, Shlomo

IPC: H04L27/34

Abstract: A headend transmitter that transmits 1024 QAM including a 256 QAM modulator (13) which has been modified to have more aggressive forward error correction processing. The 256 QAM modulator outputs 256 QAM points to a summer (16). Another data modulator (22) receives additional data (20) to be transmitted in a separate, substantially less complex constellation. This modulator processes (24) the additional data to do forward error correction thereon and then maps the encoded data into a less complex constellation such as QPSK, 16 QAM etc. The additional data constellation points are then amplified in a variable gain amplifier (32) and fed to a summer (16) where each additional data point is added by vector summation to one 256 QAM point. The output 1024 QAM point is filtered (40) and shifted (75) to the desired transmission frequency. Legacy cable modem receivers can still receive the 256 QAM point since the addition of the new data just appears to be noise which they can overcome using the parity bits encoded in the transmitted symbols. 1024 QAM cable modem receivers receive both the 256 QAM points and the new data points and output both.

公开(公告)号：WO2005050570A1

公开(公告)日：2005-06-02

申请号：PCT/IB2004/003821

申请日：2004-11-19

Applicant: ATI TECHNOLOGIES, INC ,  ATI INTERNATIONAL, SRL ,  MOREIN, Steven ,  LEFEBVRE, Laurent ,  GRUBER, Andy ,  SKENDE, Andi

Inventor： MOREIN, Steven ,  LEFEBVRE, Laurent ,  GRUBER, Andy ,  SKENDE, Andi

IPC: G06T15/00

CPC classification number: G06T1/20 ,  G06T15/005 ,  G06T15/80

Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

Abstract translation: 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作来执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中

公开(公告)号：WO2013091066A1

公开(公告)日：2013-06-27

申请号：PCT/CA2012/001127

申请日：2012-12-07

Applicant: ATI TECHNOLOGIES INC. ,  LICHMANOV, Yury

Inventor： LICHMANOV, Yury

IPC: G06F12/02 ,  G06F15/76

CPC classification number: G06F12/0888 ,  G06F12/126

Abstract: The present invention provides embodiments of methods and apparatuses for selective caching of data for inter-operations in a heterogeneous computing environment. One embodiment of a method includes allocating a portion of a first cache for caching for two or more processing elements and defining a replacement policy for the allocated portion of the first cache. The replacement policy restricts access to the first cache to operations associated with more than one of the processing elements.

Abstract translation: 本发明提供了用于在异构计算环境中用于选择性缓存用于互操作的数据的方法和装置的实施例。 方法的一个实施例包括为两个或多个处理元件分配用于高速缓存的一部分，并为所分配的第一高速缓存部分定义替换策略。 替换策略将对第一缓存的访问限制为与多个处理元件相关联的操作。

公开(公告)号：WO2007136785A3

公开(公告)日：2008-05-02

申请号：PCT/US2007011964

申请日：2007-05-17

Applicant: ATI TECHNOLOGIES INC ,  MACRI JOSEPH ,  MOREIN STEPHEN ,  LEE MING-JU E ,  CHEN LIN

Inventor： MACRI JOSEPH ,  MOREIN STEPHEN ,  LEE MING-JU E ,  CHEN LIN

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2227 ,  Y02D10/14

Abstract: Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high¬ speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.

Abstract translation: 描述了针对在模拟定时电路初始化和变得可用的时间段期间继续以低功率模式工作的存储器件和存储器控制器的实施例。 在用于高速接口的低速到高速转换操作模式期间，存储器件和存储器控制器之间的接口的定时电路锁定到正向时钟信号，并且与低速接口的继续操作同时进行 模式。 参考时钟信号被配置为以提供高速模式和低速模式并且被用作单个速率时钟的速率操作，允许相位检测和校正电路被禁用，从而允许由 从低速模式向高速模式的转变将大大降低。