公开(公告)号：EP0705043A1

公开(公告)日：1996-04-03

申请号：EP94830470.4

申请日：1994-09-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： d'Alto, Viviana ,  Mancuso, Massimo ,  Poluzzi, Rinaldo ,  Rizzotto, Gianguido

IPC: H04N9/64 ,  H04N5/21

CPC classification number: H04N9/646 ,  H03H2222/02 ,  H04N5/21

Abstract: A device for filtering video images, of the type which comprises first and second circuit portions (3,4), each having first (PFy),(PFuv) and second (CFy),(CFuv) input terminals respectively adapted to receive digitalized luminance (Y) and chrominance (U,V) components of a television signal, and an output terminal coinciding with an output terminal of the device. The first and second circuit portions (3,4) further comprise first (5), second (6) and third (8) filters, cascade coupled to one another, and a fourth filter (9), respectively.
The first (5), second (6) and third (8) filters incorporate computational circuit means which use a logic of the fuzzy type to process the digitalized luminance component (Y). The fourth filter (9) comprises, on the other hand, computational circuit means which process the digitalized chrominance components (U,V) based upon a parameter (knr) supplied from the second filter (6).

Abstract translation: 一种用于过滤视频图像的装置，包括第一和第二电路部分（3,4），每个具有分别适于接收数字化亮度的第一（PFy），（PFuv）和第二（CFy），（CFuv） （Y）和色度（U，V）分量，以及与装置的输出端重合的输出端。 第一和第二电路部分（3,4）还包括分别彼此耦合的第一（5），第二（6）和第三（8）滤波器，以及第四滤波器（9）。 第一（5），第二（6）和第三（8）滤波器包括使用模糊类型的逻辑来处理数字化亮度分量（Y）的计算电路装置。 另一方面，第四滤波器（9）包括基于从第二滤波器（6）提供的参数（knr）处理数字化色度分量（U，V）的计算电路装置。

公开(公告)号：EP0704901A1

公开(公告)日：1996-04-03

申请号：EP94830468.8

申请日：1994-09-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Mazzali, Stefano

IPC: H01L23/528 ,  H01L27/115

CPC classification number: H01L27/115 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The integrated circuit tolerant of large manufacturing defects comprising a first plurality of first conductors (CO1) made of a first material with relatively low conductivity and each having a plurality of first electrical connection points (CP) arranged along itself and a second corresponding plurality of second conductors (CO2) made of a second material with relatively high conductivity and each having a plurality of second electrical connection points (CP) arranged along itself and said plurality of first points are electrically connected to said plurality of second points respectively in such a manner as to reduce the series resistance of the first conductors and the second conductors (CO2) are interrupted between some second consecutive points (CP) in such a manner as to leave relatively large areas of the integrated circuit not traversed by the second conductors (CO2).

Abstract translation: 所述集成电路容许大的制造缺陷包括由具有相对低导电率的第一材料制成的第一多个第一导体（CO1），并且每一个具有沿其自身布置的多个第一电连接点（CP）和第二对应的多个第二导体 由具有较高导电性的第二材料制成的导体（CO 2），并且每个具有多个沿其自身布置的多个第二电连接点（CP）和所述多个第一点分别以这样的方式电连接到所述多个第二点 为了减小第一导体的串联电阻，并且第二导体（CO 2）在一些第二连续点（CP）之间被中断，以使集成电路的相对较大的区域不被第二导体（CO 2）穿过。

公开(公告)号：EP0703666A1

公开(公告)日：1996-03-27

申请号：EP94830435.7

申请日：1994-09-16

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Diazzi, Claudio ,  Martignoni, Fabrizio ,  Tarantola, Mario

IPC: H03K17/687

CPC classification number: H03K3/356113 ,  H03K17/063 ,  H03K17/161 ,  H03K17/687

Abstract: A control circuit for a power transistor (T1) is described, connected between two supply terminals (ground, V H ) in series with a load (L) and comprising a control logic circuit (LG) which produces a signal at two levels with respect to a reference terminal (ground), a level shifter (LS1) connected between the control circuit (LG) and the power transistor (T1), which produces a signal at two levels referred to the node (S1) between the power transistor (T1) and the load (L). The level shifter (LS1) comprises a flip-flop (RS) the output of which controls the power transistor (T1), and an electronic switch, for example a MOSFET transistor, connected between the "set" input (S) of the flip-flop and the node (S1) and controlled by the "reset" input (R) of the flip-flop in such a way as to be closed when the "reset" input (R) is greater, by a predetermined value, than that of the node (S1).

Abstract translation: 描述了用于功率晶体管（T1）的控制电路，其连接在与负载（L）串联的两个电源端子（接地，VH）之间，并且包括控制逻辑电路（LG），该控制逻辑电路产生两个相对于 连接在控制电路（LG）和功率晶体管（T1）之间的参考端子（接地），电平移位器（LS1），其产生在功率晶体管（T1）之间的节点（S1）的两个电平的信号， 和负载（L）。 电平移位器（LS1）包括其输出控制功率晶体管（T1）的触发器（RS），以及连接在触发器的“设置”输入（S）之间的电子开关，例如MOSFET晶体管 （S1）并且由触发器的“复位”输入（R）控制，以便当“复位”输入（R）大于预定值时被关闭，比预定值 节点（S1）的节点。

公开(公告)号：EP0572755B1

公开(公告)日：1996-03-13

申请号：EP92830281.9

申请日：1992-05-29

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Botti, Edoardo ,  Fassina, Andrea

IPC: H02H11/00 ,  H03F1/30

CPC classification number: H02H11/00 ,  H03F1/305

公开(公告)号：EP0700051A1

公开(公告)日：1996-03-06

申请号：EP94830412.6

申请日：1994-08-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Golla, Carla ,  Padoan, Silvia ,  Pascucci, Luigi

IPC: G11C16/06

CPC classification number: G11C16/3486 ,  G11C16/3459 ,  G11C16/3468

Abstract: A circuit for single-bit programming a memory word in non-volatile memory electronic devices, being of a type which comprises, for each elementary memory cell included in the word, at least one comparator (2) having a first input (3) connected after a read circuit (SA) for reading the word contents and a second input (9) receiving data corresponding to a bit to be stored into said word, and
at least one transistor (11) driven from a first output (10) of the comparator (2) to enable the logic value contained in a corresponding one of the cells to be re-programmed; and
at least one logic gate (PL4) incorporated to the comparator (2) to produce, at a second output (13), a signal (DINCOMP) to enable re-programming of the i-th cell in said word whose programming has been found incorrect by the comparator (2).

Abstract translation: 一种用于对非易失性存储器电子器件中的存储器字进行单位编程的电路，其特征在于，对于包括在该字中的每个基本存储单元，包括至少一个具有连接的第一输入（3）的比较器（2） 在用于读取字内容的读电路（SA）和接收对应于要存储到所述字中的位的数据的第二输入（9）以及从所述字的第一输出（10）驱动的至少一个晶体管（11） 比较器（2）使得包含在相应的一个单元中的逻辑值能被重新编程; 以及至少一个并入到所述比较器（2）中的逻辑门（PL4），以在第二输出端（13）产生信号（DINCOMP），以使能编程的所述单词中的第i个单元重新编程 由比较器（2）发现不正确。 $$

公开(公告)号：EP0696846A1

公开(公告)日：1996-02-14

申请号：EP94830401.9

申请日：1994-08-12

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Brianti, Francesco ,  Alini, Roberto ,  Pisati, Valerio ,  Gadducci, Paolo

IPC: H03H1/00 ,  H03H11/04

CPC classification number: H03H11/0433

Abstract: A high-pass filter in particular for high-frequency applications and of the type comprising at least one input terminal (IN) and at least one output terminal (OUT) between which is defined a transfer function (FdT) and is inserted a biquadratic cell (18) incorporating a series of transconductance stages (2, 3, 4, 5) comprises a generator circuit (29) of variable currents (i K1 , i K2 ) connected between a pair of stages (2, 3) of the biquadratic cell (18) and a voltage reference (GND). Said generator allows introduction of programmable zeroes in the transfer function (FdT) of the filter (20).

Abstract translation: 一种高通滤波器，特别是用于高频应用，并且包括至少一个输入端（IN）和至少一个输出端（OUT）的类型，其间被定义为传输函数（FdT），并且插入一个二次电池 包括一系列跨导级（2,3,4,5）的（18）包括连接在所述二次电池（18）的一对级（2,3）之间的可变电流（iK1，iK2）的发生器电路（29） ）和参考电压（GND）。 所述发生器允许在滤波器（20）的传递函数（FdT）中引入可编程零点。 $$

公开(公告)号：EP0696054A1

公开(公告)日：1996-02-07

申请号：EP94830331.8

申请日：1994-07-04

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Ferla, Giuseppe ,  Frisina, Ferruccio

IPC: H01L21/336

CPC classification number: H01L29/66719 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66712 ,  Y10S148/126

Abstract: A process for the manufacturing of high-density MOS-technology power devices comprises the steps of: forming a conductive insulated gate layer (8) on a surface of a lightly doped semiconductor material layer (2) of a first conductivity type; forming an insulating material layer (11) over the insulated gate layer (8); selectively removing the insulating material layer (11) and the underlying insulated gate layer (8) to form a plurality of elongated windows (15) having two elongated edges (17) and two short edges (18), delimiting respective uncovered surface stripes (16) of the semiconductor material layer (2); implanting a high dose of a first dopant of the first conductivity type along two directions which lie in a plane transversal to said elongated windows (15) and orthogonal to the semiconductor material layer (2) surface, and which are substantially simmetrically tilted of a first prescribed angle (A1,A2) with respect to a direction (T) orthogonal to the semiconductor material layer (2) surface, the first angle (A1,A2) depending on the overall thickness of the insulated gate layer (8) and of the insulating material layer (11) to prevent the first dopant from being implanted in a central stripe of said uncovered surface stripes (16), to form pairs of heavily doped elongated source regions (6) of the first conductivity type which extend along said two elongated edges (17) of each elongated window (15) and which are separated by said central stripe; implanting a low dose of a second dopant of a second conductivity type along two directions which lie in said plane, and which are substantially simmetrically tilted of a second prescribed angle (A3,A4) with respect to said orthogonal direction (T), to form doped regions of the second conductivity type each comprising two lightly doped elongated channel regions (5) extending under the two elongated edges (17) of each elongated window (15); implanting a high dose of a third dopant of the second conductivity type substantially along said orthogonal direction (T), the insulating material layer (11) acting as a mask, to form heavily doped regions (4) substantially aligned with the edges (17,18) of the elongated windows (15).

Abstract translation: 制造高密度MOS技术功率器件的方法包括以下步骤：在第一导电类型的轻掺杂半导体材料层（2）的表面上形成导电绝缘栅层（8）; 在所述绝缘栅极层（8）上形成绝缘材料层（11）; 选择性地去除绝缘材料层（11）和下面的绝缘栅极层（8）以形成具有两个细长边缘（17）和两个短边缘（18）的多个细长窗口（15），其限定相应的未覆盖的表面条纹 ）半导体材料层（2）; 沿着位于与所述细长窗（15）横向并垂直于所述半导体材料层（2）表面的平面的两个方向上沿着两个方向植入高剂量的第一导电类型的第一掺杂剂，并且其基本上相对于第一 相对于与半导体材料层（2）表面正交的方向（T）的规定角度（A1，A2），取决于绝缘栅极层（8）的总厚度的第一角度（A1，A2） 绝缘材料层（11），以防止第一掺杂剂注入到所述未覆盖的表面条纹（16）的中心条纹中，以形成沿着所述两个细长延伸的第一导电类型的重掺杂细长源区域（6） 每个细长窗口（15）的边缘（17）并且由所述中心条带分隔开; 沿着位于所述平面中的两个方向植入低剂量的第二导电类型的第二掺杂剂，并且相对于所述正交方向（T）基本上相对于第二规定角度（A3，A4）倾斜倾斜以形成 所述第二导电类型的掺杂区域包括在每个细长窗口（15）的两个细长边缘（17）下方延伸的两个轻掺杂的细长沟道区域（5）。 基本上沿着所述正交方向（T）注入高剂量的第二导电类型的第三掺杂剂，所述绝缘材料层（11）用作掩模，以形成基本上与所述边缘（17）相对准的重掺杂区域（4） 18）。 $$

公开(公告)号：EP0487133B1

公开(公告)日：1996-02-07

申请号：EP91202916.2

申请日：1991-11-09

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Brambilla, Davide ,  Brasca, Guido ,  Botti, Edoardo

IPC: H03F3/30 ,  H03F1/02

CPC classification number: H03F1/0277 ,  H03F3/3081

公开(公告)号：EP0695030A1

公开(公告)日：1996-01-31

申请号：EP94830390.4

申请日：1994-07-29

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Pisati, Valerio ,  Alini, Roberto ,  Castello, Rinaldo ,  Vai, Gianfranco

IPC: H03G1/00 ,  H03F1/08 ,  H03H11/04

CPC classification number: H03F3/45883 ,  H03F3/45286 ,  H03F3/45807 ,  H03F2203/45648 ,  H03G1/0023

Abstract: A controlled gain transconductor (20) which comprises a transconductance stage (3) having at least two input terminals (I1, I2) and at least two output terminals (O1, O2), an active load (4) connected to the output terminals of the transconductance stage and a control circuit (5) for the active load (4) conneccted between said output terminals (O1, O2) and the active load (4).
Also provided is a circuit portion (10) being a replica of the transconductance stage (3), the active load (4) and the control circuit (5). This replicated portion (10) has an output connected to the control circuit (5) of the transconductor (20) to provide a predetermined voltage value (Vc) required for adjusting the DC gain of the device.

Abstract translation: 一种受控增益跨导体（20），包括具有至少两个输入端（I1，I2）和至少两个输出端（O1，O2）的跨导级（3），连接到输出端 所述跨导级和用于所述输出端子（O1，O2）和所述有源负载（4）之间连接的有源负载（4）的控制电路（5）。 还提供了作为跨导级（3），有源负载（4）和控制电路（5）的复制品的电路部分（10）。 该复制部分（10）具有连接到跨导体（20）的控制电路（5）的输出端，以提供调节器件的直流增益所需的预定电压值（Vc）。 $$

公开(公告)号：EP0544628B1

公开(公告)日：1996-01-10

申请号：EP92830588.7

申请日：1992-10-28

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Maiocchi, Giuseppe

IPC: H02P6/00

CPC classification number: H02P6/22 ,  H02P6/185 ,  H02P6/30