公开(公告)号：EP0492375B1

公开(公告)日：1995-09-20

申请号：EP91121651.3

申请日：1991-12-17

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Brambilla, Davide ,  Botti, Edoardo

IPC: H02H7/20

CPC classification number: H03K17/04113 ,  H03K17/0826

公开(公告)号：EP0492373A1

公开(公告)日：1992-07-01

申请号：EP91121649.7

申请日：1991-12-17

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Brambilla, Davide ,  Stefani, Frabrizio

IPC: H03F3/45 ,  H03F3/343

CPC classification number: H03F3/45479 ,  H03F3/3437

Abstract: Intrinsic offset recovery circuit particularly for amplifiers, which comprises an input differential amplifier constituted by a first PNP transistor (1), by a second PNP transistor (2), by a third NPN transistor (3), by a fourth NPN transistor (4) and by a first constant-current source (8), and a unitary-gain output stage (10). The recovery circuit furthermore comprises, as connection between the input differential amplifier and the unitary-gain output stage (10), a gain stage which comprises a fifth NPN transistor (6) which is connected to the output of the input differential amplifier and is connected to a sixth NPN transistor (7) and to a seventh PNP transistor (11). The seventh transistor (11) is connected to the sixth transistor (7). The seventh transistor (11) and the sixth transistor (7) are connected to the unitary-gain output stage (10).

Abstract translation: 专用于放大器的固有偏移恢复电路，其包括由第一PNP晶体管（1）由第二PNP晶体管（2）由第三NPN晶体管（3）由第三NPN晶体管（3）由第四NPN晶体管（4）构成的输入差分放大器， 以及第一恒定电流源（8）和单一增益输出级（10）。 恢复电路还包括作为输入差分放大器和单位增益输出级（10）之间的连接的增益级，其包括连接到输入差分放大器的输出并被连接的第五NPN晶体管（6） 到第六NPN晶体管（7）和第七PNP晶体管（11）。 第七晶体管（11）连接到第六晶体管（7）。 第七晶体管（11）和第六晶体管（7）连接到单一增益输出级（10）。

公开(公告)号：EP0760555A1

公开(公告)日：1997-03-05

申请号：EP95830369.5

申请日：1995-08-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Brambilla, Davide ,  Nebuloni, Daniela ,  Rossi, Giorgio ,  Lecce, Sergio

IPC: H03F3/345 ,  G05F3/26

CPC classification number: H03F3/345 ,  G05F3/267

Abstract: A current generator circuit with controllable frequency response is of a type which comprises at least one current mirror formed of MOS transistors, being powered through a terminal held at a constant voltage, having an input leg through which a reference current (I1) is driven by a first current generator (G1), and having an output leg for generating, on an output terminal (OUT) of the mirror, a mirrored current (I out ) which is proportional to the reference current (I1). The input leg includes at least a first transistor (M1) which is diode-connected and has a control terminal (Ga1) coupled to a corresponding terminal (Ga2) of a second transistor (M2) included in the output leg.
In accordance with the invention, the mirror circuit further comprises an impedance matching means (3) connected across the control terminals (Ga1 and Ga2) of the first and second transistors and configured to hold the same voltage value at both terminals (Ga1 and Ga2). The impedance matching means (3) has an adjustable output impedance, specifically lower in value than the value to be had without this means. It functions to regulate the impedance on the control node (Ga2) of the second transistor (M2).
The invention is equally applicable to N-channel and P-channel MOS transistors.
Advantageously, the reference current can be varied by an external signal which is a function of the output signal, to provide feedback regulating features.

Abstract translation: 具有可控频率响应的电流发生器电路是一种类型，其包括由MOS晶体管形成的至少一个电流镜，通过保持在恒定电压的端子供电，具有输入支路，参考电流（I1）通过该输入支路由 第一电流发生器（G1），并且具有用于在所述反射镜的输出端子（OUT）上产生与所述参考电流（I1）成比例的镜像电流（Iout）的输出支路。 输入支路至少包括二极管连接的第一晶体管（M1），并且具有耦合到包括在输出支路中的第二晶体管（M2）的相应端子（Ga2）的控制端子（Ga1）。 根据本发明，镜电路还包括连接在第一和第二晶体管的控制端（Ga1和Ga2）两端的阻抗匹配装置（3），并被配置为在两端（Ga1和Ga2）处保持相同的电压值， 。 阻抗匹配装置（3）具有可调节的输出阻抗，具体值低于没有这种方法的值。 它用于调节第二晶体管（M2）的控制节点（Ga2）上的阻抗。 本发明同样适用于N沟道和P沟道MOS晶体管。 有利地，参考电流可以通过作为输出信号的函数的外部信号来改变，以提供反馈调节特征。

公开(公告)号：EP0487133B1

公开(公告)日：1996-02-07

申请号：EP91202916.2

申请日：1991-11-09

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Brambilla, Davide ,  Brasca, Guido ,  Botti, Edoardo

IPC: H03F3/30 ,  H03F1/02

CPC classification number: H03F1/0277 ,  H03F3/3081

公开(公告)号：EP0487133A3

公开(公告)日：1992-09-09

申请号：EP91202916.2

申请日：1991-11-09

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Brambilla, Davide ,  Brasca, Guido ,  Botti, Edoardo

IPC: H03F3/30 ,  H03F1/02

CPC classification number: H03F1/0277 ,  H03F3/3081

Abstract: The amplifier comprises a first and a second amplifier block (A1, A2) of opposite phase driven by a single input signal (Vin) and having its outputs (Vout1, Vout2) connected to the two terminals of a load (L). It also comprises circuit means (I1, I2) to disable one (A2) of the said amplifier blocks (A1, A2) when the absolute value of the input signal is less than a predetermined threshold level. A passive feedback system (R1, R2, R3, R4) capable of maintaining the amplifier gain constant is located between the aforesaid terminals of the load (L) and the inputs to the two amplifier blocks (A1, A2).

公开(公告)号：EP0492373B1

公开(公告)日：1996-02-07

申请号：EP91121649.7

申请日：1991-12-17

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Brambilla, Davide ,  Stefani, Frabrizio

IPC: H03F3/45 ,  H03F3/343

CPC classification number: H03F3/45479 ,  H03F3/3437

公开(公告)号：EP0492375A1

公开(公告)日：1992-07-01

申请号：EP91121651.3

申请日：1991-12-17

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Brambilla, Davide ,  Botti, Edoardo

IPC: H02H7/20

CPC classification number: H03K17/04113 ,  H03K17/0826

Abstract: Voltage/current characteristics control circuit particularly for protecting power transistors, which comprises at least one power transistor; the emitter terminal of a second transistor (5) is directly connected to the output of the power transistor; the emitter terminal of a first transistor (4) is connected to the output of the power transistor by means of a first resistor (6). The collector terminal and the base terminal of the second transistor (5) are connected to a current source (3). The base terminal of the first transistor (4) is connected to the base terminal of the second transistor (5), and the circuit furthermore comprises a protection circuitry (2). The circuitry is connected to the collector terminal of the first transistor (4) through a differential stage which comprises a third transistor (9) and a fourth transistor (10); the third transistor (9) and fourth transistor (10) have a respective second resistor (12) and third resistor (13) arranged in series. Divider means (14) are furthermore provided and are interposed between the input terminal of the power transistor and the base terminals of the third transistor (9) and fourth transistor (10).

Abstract translation: 电压/电流特性控制电路，特别是用于保护功率晶体管，其包括至少一个功率晶体管; 第二晶体管（5）的发射极端子直接连接到功率晶体管的输出端; 第一晶体管（4）的发射极端子通过第一电阻器（6）连接到功率晶体管的输出端。 第二晶体管（5）的集电极端子和基极端子连接到电流源（3）。 第一晶体管（4）的基极连接到第二晶体管（5）的基极，并且电路还包括保护电路（2）。 电路通过包括第三晶体管（9）和第四晶体管（10）的差分级与第一晶体管（4）的集电极端子相连。 第三晶体管（9）和第四晶体管（10）具有串联布置的相应的第二电阻器（12）和第三电阻器（13）。 此外设置分频器装置（14）并且插入在功率晶体管的输入端子和第三晶体管（9）和第四晶体管（10）的基极端子之间。

公开(公告)号：EP0725442A1

公开(公告)日：1996-08-07

申请号：EP95830024.6

申请日：1995-01-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Brambilla, Davide ,  Botti, Edoardo ,  Ferrari, Paolo

IPC: H01L27/00 ,  H01L27/02

CPC classification number: H01L27/0664

Abstract: A monolithic output stage which is self-protected against the occurrence of incidental latch-up phenomena and integrated in a portion of a semiconductor material chip which is isolated by a peripheral barrier structure linked electrically to a terminal (Vcc), specifically a supply terminal being applied thereto a constant voltage (+Vcc), has the barrier structure coupled to the terminal (Vcc) through a forward biased diode (D1) from the terminal (Vcc).
The integrated barrier structure is formed within a region (21'') having a first type of conductivity, and comprises a heavily doped well (29) having the first type of conductivity and a substantially annular shape and contacting a large surface of the chip (22). This structure is characterized in that, in at least one portion thereof close to contact regions (S) for connection to said terminal (Vcc), the barrier well (29) is split into first and second heavily doped concentrical regions (29' and 29'') having the first type of conductivity. The barrier structure further comprises, located at said portion, an intermediate region (30) which is less heavily doped and also has the first type of conductivity, and a surface region (31) with a second type of conductivity located within said intermediate region.
The invention preferably involves a power output stage including a vertical PNP transistor isolated by said barrier well.

Abstract translation: 单片输出级，其自发保护，防止偶然的闩锁现象的发生并且集成在由与端子（Vcc）电连接的外围阻挡结构隔离的半导体材料芯片的一部分中，特别是电源端子 施加恒定电压（+ Vcc），通过来自端子（Vcc）的正向偏置二极管（D1）将阻挡结构耦合到端子（Vcc）。 所述集成阻挡结构形成在具有第一类型导电性的区域（21“）内，并且包括具有第一类型导电性和基本环形形状并与芯片的大表面接触的重掺杂阱（29） 22）。 该结构的特征在于，在靠近与所述端子（Vcc）连接的接触区域（S）的至少一部分中，阻挡阱（29）被分成第一和第二重掺杂的同心区域（29'和29 “）具有第一类导电性。 所述阻挡结构还包括位于所述部分的中间区域（30），所述中间区域（30）的重掺杂性也具有第一类型的导电性，以及具有位于所述中间区域内的第二类型导电性的表面区域（31）。 本发明优选地包括功率输出级，其包括由所述屏障阱隔离的垂直PNP晶体管。

公开(公告)号：EP0720023A1

公开(公告)日：1996-07-03

申请号：EP94830592.5

申请日：1994-12-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Brambilla, Davide ,  Capodivacca, Giovanni ,  Stefani, Fabrizio

IPC: G01R31/00 ,  G01R31/316

CPC classification number: G01R31/2853

Abstract: A method of checking the integrity of an electric power connect (7) between a contact pad (5) of an integrated circuit (2) and a corresponding contact pin (8) in an electronic power device including two final power stages (3,4) powered from respective discrete contact pads (5,6) connected by means of electric power connects (7,13) to respective contact pins (8,9), comprises the steps of,

providing a resistive connection (14) between said two contact pads (5,6),
bringing a first final power stage (3), powered from the first contact pad (5), to a conduction state,
measuring the potential difference between the two contact pins (8,9) connected to said two contact pads (5,6), and
comparing said potential difference with a predetermined nominal potential difference.

Abstract translation: 一种在包括两个最终功率级（3,4）的电子功率器件中检查集成电路（2）的接触焊盘（5）和相应接触引脚（8）之间的电力连接（7）的完整性的方法， ）由通过电力连接（7,13）连接到相应的接触引脚（8,9）的相应的分立接触焊盘（5,6）供电，包括以下步骤：在所述两个接触件之间提供电阻连接（14） 将由第一接触焊盘（5）供电的第一最终功率级（3）引导到导通状态，测量连接到所述两个接触焊盘的两个接触针（8,9）之间的电势差 接触垫（5,6），并将所述电位差与预定的标称电位差进行比较。

公开(公告)号：EP0487133A2

公开(公告)日：1992-05-27

申请号：EP91202916.2

申请日：1991-11-09

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Brambilla, Davide ,  Brasca, Guido ,  Botti, Edoardo

IPC: H03F3/30 ,  H03F1/02

CPC classification number: H03F1/0277 ,  H03F3/3081

Abstract: The amplifier comprises a first and a second amplifier block (A1, A2) of opposite phase driven by a single input signal (Vin) and having its outputs (Vout1, Vout2) connected to the two terminals of a load (L). It also comprises circuit means (I1, I2) to disable one (A2) of the said amplifier blocks (A1, A2) when the absolute value of the input signal is less than a predetermined threshold level. A passive feedback system (R1, R2, R3, R4) capable of maintaining the amplifier gain constant is located between the aforesaid terminals of the load (L) and the inputs to the two amplifier blocks (A1, A2).

Abstract translation: 所述放大器包括第一和由单个输入信号（Vin）和从动相反的相位的第二放大器块（A1，A2），其具有其连接到负载（L）的两个端子输出（VOUT1，Vout2的）。 它因此包括电路装置（I1，I2）来禁用所述放大器块中的一个（A2）（A1，A2）当输入信号的绝对值小于预定阈值水平。 无源反馈系统（R1，R2，R3，R4），其能够保持放大器增益常数位于负载（L）的上述端子与输入到两个放大器块（A1，A2）之间的。