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    Packet Synchronization Information Peeking
    112.
    发明申请
    Packet Synchronization Information Peeking 有权

    公开(公告)号：US20220022132A1

    公开(公告)日：2022-01-20

    申请号：US16928356

    申请日：2020-07-14

    Applicant: Silicon Laboratories Inc.

    Inventor： Jere M. Knaappila

    IPC: H04W52/02 ,  H04W56/00

    Abstract: A device, method and software program that allows a network device to remain synchronized to a master device while minimizing its own power consumption is disclosed. The network device exits a low power mode at regular intervals in order to receive a synchronous communication from a master device. Once the network device has received enough information to confirm that this synchronous communication is from the correct master device, the network device may then return to the low power mode, even before the entirety of the synchronous communication has been received. This may reduce the time that the network device is in the active state by more than 90% in certain instances.

    End node spectrogram compression for machine learning speech recognition
    113.
    发明授权
    End node spectrogram compression for machine learning speech recognition 有权

    公开(公告)号：US11227614B2

    公开(公告)日：2022-01-18

    申请号：US16898806

    申请日：2020-06-11

    Applicant: Silicon Laboratories Inc.

    Inventor： Antonio Torrini ,  Sebastian Ahmed

    IPC: G10L19/02 ,  G10L25/18

    Abstract: A system and method of recording and transmitting compressed audio signals over a network is disclosed. The end node device first converts the audio signal to a spectrogram, which is commonly used by machine learning algorithms to perform speech recognition. The end node device then compresses the spectrogram prior to transmission. In certain embodiments, the compression is performed using Discrete Cosine Transforms (DCT). Furthermore, in some embodiments, the DCT is performed on the difference between two columns of the spectrogram. Further, in some embodiments, a function that replaces values below a predetermined threshold with zeroes in the Encoded Spectrogram is utilized. These functions may be performed in hardware or software.

    Variable rate sampling for AGC in a bluetooth receiver using connection state and access address field
    114.
    发明授权
    Variable rate sampling for AGC in a bluetooth receiver using connection state and access address field 有权

    公开(公告)号：US11206122B1

    公开(公告)日：2021-12-21

    申请号：US17106111

    申请日：2020-11-29

    Applicant: Silicon Laboratories, Inc.

    Inventor： Sriram Mudulodu

    IPC: H04L7/00 ,  H04B1/12 ,  H03M1/12

    Abstract: A Bluetooth receiver has an RF front end which has a gain control input, the RF front end converting wireless packets into a baseband signal which is coupled to the input of an analog to digital converter (ADC). A clock generator provides a clock coupled to the ADC, and an AGC processor performs an AGC process to provide a gain which places the baseband symbols in a range that is less than 90% of the input dynamic range of the ADC. When in a connected state, the clock generator provides a clock which is slower than is required to complete the AGC process during a preamble interval, and the AGC process uses a few initial bits of the address field. The remaining bits of the address field is compared with the corresponding address bits of the receiver to determine whether to receive the packet.

    System and method of improving blocking immunity of radio frequency transceiver front end
    116.
    发明授权
    System and method of improving blocking immunity of radio frequency transceiver front end 有权

    公开(公告)号：US11196385B2

    公开(公告)日：2021-12-07

    申请号：US16793985

    申请日：2020-02-18

    Applicant: Silicon Laboratories Inc.

    Inventor： Ruifeng Sun ,  Ricky Setiawan ,  Ben Wee-Guan Tan

    IPC: H03F1/02 ,  H03F3/21 ,  H03F3/193

    Abstract: A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.

    Secure software system for microcontroller or the like and method therefor
    117.
    发明授权
    Secure software system for microcontroller or the like and method therefor 有权

    公开(公告)号：US11188656B2

    公开(公告)日：2021-11-30

    申请号：US16047261

    申请日：2018-07-27

    Applicant: Silicon Laboratories Inc.

    Inventor： Steven Jan Anne Ward Cooreman

    IPC: G06F21/57 ,  G06F8/41 ,  G06F9/30 ,  G06F21/54

    Abstract: In one form, a software system includes a first non-transitory computer readable medium storing a source code program, a second computer readable medium, and a compiler. The first non-transitory computer readable medium includes a first function having a return type greater than a native width of a target processor, and a second function that calls the first function and that conditionally branches based on comparing a returned value from the first function to an expected value, wherein the expected value has first and second portions that are not equal to zero and are not equal to each other. The compiler converts the source code program in the first non-transitory computer readable medium into a machine language program for storage in the second computer readable medium. The compiler optimizes the source code program by selectively combining a set of redundant machine language instructions into a smaller set of machine language instructions.

    Neural Network Inference and Training Using A Universal Coordinate Rotation Digital Computer
    119.
    发明申请
    Neural Network Inference and Training Using A Universal Coordinate Rotation Digital Computer 有权

    公开(公告)号：US20210350221A1

    公开(公告)日：2021-11-11

    申请号：US16866994

    申请日：2020-05-05

    Applicant: Silicon Laboratories Inc.

    Inventor： Javier Elenes

    IPC: G06N3/08 ,  G06F7/544 ,  G06N3/04

    Abstract: A system and method of implementing a neural network with a non-linear activation function is disclosed. A Universal Coordinate Rotation Digital Computer (CORDIC) is used to implement the activation function. Advantageously, the CORDIC is also used during training for back propagation. Using a CORDIC, activation functions such as hyperbolic tangent and sigmoid may be implemented without the use of a multiplier. Further, the derivatives of these functions, which are needed for back propagation, can also be implemented using the CORDIC.

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