公开(公告)号：US20020146042A1

公开(公告)日：2002-10-10

申请号：US10039765

申请日：2001-11-07

Applicant: STMicroelectronics S.A.

Inventor： Franck Roche ,  Pierre Tarayre

IPC: H04J003/06

CPC classification number: G06F13/4286

Abstract: The method is for transmitting data between two devices via a clock wire or line and at least one data wire or line. The clock wire is maintained by default on a logic value A, and each device is capable of tying the clock wire to an electric potential representing a logic value B that is the opposite of A. According to the method, both devices tie the clock wire to B when a datum is transmitted, the device to which the datum is sent does not release the clock wire while it has not read the datum, and the device sending the datum maintains the datum on the data wire at least until an instant when the clock wire is released by the device to which the datum is sent. The method is particularly applicable to communication between a microcomputer and a microprocessor.

Abstract translation: 该方法用于经由时钟线或线路和至少一条数据线或线路在两个设备之间传输数据。 时钟线在默认情况下保持在逻辑值A上，并且每个器件能够将时钟线绑定到表示与A相反的逻辑值B的电位。根据该方法，两个器件将时钟线 到B时，发送数据时，发送数据的设备在没有读取数据的情况下不会释放时钟线，并且发送数据的设备至少在数据线上维护数据，直到当时 时钟线由发送基准的设备释放。 该方法特别适用于微型计算机与微处理器之间的通信。

公开(公告)号：US20020145411A1

公开(公告)日：2002-10-10

申请号：US10082785

申请日：2002-02-25

Applicant: STMicroelectronics S.A.

Inventor： Philippe Sirito-Olivier

IPC: G05F003/16

CPC classification number: G05F3/267 ,  G05F3/262 ,  G05F3/265

Abstract: A current source includes a current mirror and a core connected together between two supply terminals. The current mirror comprises a pilot transistor and first and second recopy transistors. The core comprises first and second transistors and a resistance. The first transistor and the first recopy transistor are connected together to form a first branch. The resistance and the second recopy transistor are connected together to form a second branch. The pilot transistor and the second transistor are connected together to form a third branch. These branches are connected between the two supply terminals. The first transistor is linked to the second branch between the resistance and the second recopy transistor. The second transistor is connected to the first branch between the first core transistor and the first recopy transistor.

Abstract translation: 电流源包括电流镜和连接在两个电源端之间的芯。 电流镜包括导频晶体管和第一和第二复现晶体管。 芯包括第一和第二晶体管和电阻。 第一晶体管和第一复读晶体管连接在一起以形成第一分支。 电阻和第二复读晶体管连接在一起以形成第二分支。 引导晶体管和第二晶体管连接在一起形成第三分支。 这些分支连接在两个供电端子之间。 第一晶体管连接到电阻和第二复读晶体管之间的第二分支。 第二晶体管连接到第一核心晶体管和第一复现晶体管之间的第一分支。

公开(公告)号：US20020144182A1

公开(公告)日：2002-10-03

申请号：US09826427

申请日：2001-04-03

Applicant: STMicroelectronics S.A.

Inventor： Didier Cavalli

IPC: H04L001/22

CPC classification number: G06F9/4812 ,  G06F13/24

Abstract: A microprocessor is for detecting an interrupt request during execution of a program, saving contextual data elements of the program being executed, sending an interrupt acknowledge signal, and jumping to an interrupt subroutine if the interrupt request is still present after saving the contextual data. Otherwise, the microprocessor resumes execution of the interrupted program.

Abstract translation: 微处理器用于在程序执行期间检测中断请求，如果中断请求在保存上下文数据之后仍然存在，则保存正在执行的程序的上下文数据元素，发送中断确认信号和跳转到中断子程序。 否则，微处理器恢复中断程序的执行。

公开(公告)号：US20020143837A1

公开(公告)日：2002-10-03

申请号：US10035033

申请日：2001-12-28

Applicant: STMicroelectronics S.A.

Inventor： Olivier Duborgel

IPC: G06F007/38

CPC classification number: G06F7/5095 ,  G06F7/5443

Abstract: The microarchitecture of the arithmetic unit includes two cascaded N bit adders to provide an N bits result in an accumulator. The arithmetic unit also includes a carry save adder, followed by an adder, which, along with the accumulator, are extended to Nnull1 bits. A circuit for determining the output carry value associated with the result is also provided.

Abstract translation: 算术单元的微架构包括两个级联的N位加法器，以在累加器中提供N位结果。 算术单元还包括进位保存加法器，后跟一个加法器，它与累加器一起扩展到N + 1位。 还提供了用于确定与结果相关联的输出进位值的电路。

公开(公告)号：US20020142519A1

公开(公告)日：2002-10-03

申请号：US10081296

申请日：2002-02-20

Applicant: STMICROELECTRONICS S.A.

Inventor： Philippe Coronel ,  Francois Leverd ,  Paul Ferreira

IPC: H01L021/44

CPC classification number: H01L21/76897 ,  H01L21/76831 ,  H01L21/76841

Abstract: The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.

Abstract translation: 本发明涉及一种用于保护集成电路中的晶体管栅格的方法，用于制造跨越栅极的局部互连焊盘和形成在其上的硅衬底。 该方法包括在晶体管栅格上施加双电介质传导层，其中添加多晶硅层以便使用选择性原理，考虑到多晶硅相对于本地互连衬垫是 形成。 此外，根据本发明的方法，可以预先在晶体管和栅极的有源区上施加硅化处理。

公开(公告)号：US20020130387A1

公开(公告)日：2002-09-19

申请号：US10055710

申请日：2002-01-22

Applicant: STMicroelectronics S.A.

Inventor： Jean-Francois Carpentier

IPC: H01L029/00

CPC classification number: H01L28/10 ,  H01F2017/0046 ,  H01F2021/125 ,  H01L27/08

Abstract: Semiconductor device comprising a metal circuit with two parts wound into spirals which are formed such that the branches of one of the parts and the corresponding branches of the other part lie on either side of a median longitudinal region and are symmetrical with respect to this region. A common junction connects the inner ends of the parts and lies across the median longitudinal region and the intermediate junctions between the branches of one of the parts pass above or below the intermediate junctions between the branches of the other part. A common external connection is connected to the common junction and separate external connection are connected respectively to the outer ends of the wound parts. The wound parts constitute two symmetrical metal windings formed between the common connection and the separate connection, respectively, and constituting symmetrical inductors.

Abstract translation: 半导体装置包括具有卷绕成螺旋形的两个部分的金属电路，其形成为使得其中一个部分的分支和另一部分的相应分支的分支位于中间纵向区域的两侧，并且相对于该区域是对称的。 公共接头连接部件的内端并跨越中间纵向区域，并且其中一个部件的分支之间的中间接合点通过另一部分的分支之间的中间接合点的上方或下方。 共同的外部连接连接到公共接头，分离的外部连接分别连接到伤口部分的外端。 绕线部分分别形成在公共连接和分离连接之间形成的对称金属绕组，并构成对称电感器。

公开(公告)号：US20020129234A1

公开(公告)日：2002-09-12

申请号：US09995251

申请日：2001-11-27

Applicant: STMicroelectronics S.A.

Inventor： Franck Roche ,  Pascal Narche ,  Ludovic Ruat

IPC: G06F009/00

CPC classification number: G06F11/2273 ,  G01R31/31701 ,  G01R31/31719

Abstract: A microprocessor includes a counter having a counting input and a reset input. The counting input is coupled to a first terminal of the microprocessor for the selection of an operating mode thereof by application of a predetermined number of pulses to the first terminal. The reset input of the counter is driven by a control signal present on a second terminal of the microprocessor. The control signal is maintained by default at a first logic value ensuring the maintaining at zero of the counter during the initialization period by a circuit internal or external the microprocessor. Immunity against electromagnetic perturbations causing the microprocessor to enter into the test mode is provided.

Abstract translation: 微处理器包括具有计数输入和复位输入的计数器。 计数输入耦合到微处理器的第一端，用于通过向第一终端施加预定数量的脉冲来选择其操作模式。 计数器的复位输入由存在于微处理器的第二端子上的控制信号驱动。 控制信号默认维持在第一逻辑值，确保在初始化期间通过内部或外部微处理器的电路将计数器保持在零。 提供了防止导致微处理器进入测试模式的电磁扰动的抗扰度。

公开(公告)号：US20020116596A1

公开(公告)日：2002-08-22

申请号：US09915761

申请日：2001-07-26

Applicant: STMicroelectronics S.A.

Inventor： Jose Sanches ,  Marco Cornero ,  Miguel Santana ,  Philippe Guillaume ,  Jean-Marc Daveau ,  Thierry Lepley ,  Pierre Paulin ,  Michel Harrand

IPC: G06F009/30 ,  G06F012/00

CPC classification number: G06F9/3814 ,  G06F9/3802 ,  G06F9/3853 ,  G06F9/3885

Abstract: A digital signal processor is designed to execute variable-sized instructions that may include up to N elementary instruction codes. The processor comprises a memory program comprising I individually addressable, parallel-connected memory banks in which the codes of a program are recorded in an interlaced fashion, and a circuit for reading the program memory arranged to read a code in each of the I memory banks during a cycle for reading an instruction. A cycle for reading an instruction in the program memory includes reading a sequence of codes that includes the instruction code or codes to be read and can also include codes, belonging to a following instruction, that are filtered before the instruction is applied to execution units. The program memory of the digital signal processor does not include any no-operation type codes.

Abstract translation: 数字信号处理器被设计为执行可包括多达N个基本指令代码的可变大小的指令。 处理器包括存储器程序，其包括I个可寻址的并行连接的存储器组，其中以隔行方式记录程序的代码，以及用于读取布置成读取每个I存储体中的代码的程序存储器的电路 在读取指令的周期中。 用于读取程序存储器中的指令的循环包括读取包括要读取的指令代码或代码的代码序列，并且还可以包括属于后续指令的代码，该代码在指令被应用于执行单元之前被过滤。 数字信号处理器的程序存储器不包括任何无操作类型的代码。

公开(公告)号：US20020113643A1

公开(公告)日：2002-08-22

申请号：US09938289

申请日：2001-08-23

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: H03B001/00

CPC classification number: H03K5/1252

Abstract: A filtering circuit includes circuits for delivering first and second ramp-shaped signals when a logic signal to be filtered changes values, and includes logic circuits each with a switching threshold, for receiving the ramp-shaped signals. A memory unit delivers an output signal having a first value when outputs of the logic circuits have a first pair of values, and delivers a second value when the outputs of the logic circuits have a second pair of values. The filtering circuit may be applied to the filtering of an external clock signal in serial type memory devices.

Abstract translation: 滤波电路包括当待滤波的逻辑信号改变值时递送第一和第二斜坡形信号的电路，并且包括各自具有切换阈值的逻辑电路，用于接收斜坡形状的信号。 当逻辑电路的输出具有第一对值时，存储器单元递送具有第一值的输出信号，并且当逻辑电路的输出具有第二对值时传送第二值。 滤波电路可以应用于串行型存储器件中的外部时钟信号的滤波。

公开(公告)号：US20020113535A1

公开(公告)日：2002-08-22

申请号：US09997195

申请日：2001-11-28

Applicant: STMicroelectronics S.A.

Inventor： Franck Roche ,  Thierry Bouquier

IPC: H01J027/00

CPC classification number: G06F11/2236

Abstract: A microprocessor may be switchable between a normal mode and a test mode for performing a test program and may include a central processing unit (CPU) for saving contextual data in a stack of the microprocessor at the time of switching to the test mode. The CPU may deliver, at the beginning of the test program and on an input/output port, contextual data present in the stack beginning with the top of the stack. The CPU may also decrement a stack pointer by a value corresponding to a number of contextual data delivered.

Abstract translation: 微处理器可以在正常模式和用于执行测试程序的测试模式之间切换，并且可以包括用于在切换到测试模式时将上下文数据保存在微处理器的堆栈中的中央处理单元（CPU）。 CPU可以在测试程序开始时和在输入/输出端口上递送以堆栈顶部开头的堆栈中存在的上下文数据。 CPU也可以将堆栈指针减少与传递的上下文数据的数量相对应的值。