公开(公告)号：KR1020070060882A

公开(公告)日：2007-06-13

申请号：KR1020050121031

申请日：2005-12-09

Applicant: 한국전자통신연구원

Inventor： 이상우 ,  전용성 ,  김기영 ,  장종수

IPC: H04L9/30 ,  H04L9/28 ,  H04L9/08 ,  H04L9/00

CPC classification number: H04L9/0631 ,  H04L2209/122

Abstract: An apparatus and a method of ARIA encoding/decoding and a method for generating an initial key for the same are provided to reduce a size of a circuit by performing a substitution operation through different kinds of four S boxes. An apparatus of ARIA encoding/decoding iteratively includes a first register(12), a second register(13), an XOR processor(14), a substituting unit(15), a diffusing unit(16), and a controlling unit(18). The first register stores input data or an intermediate calculation value according to a first control signal. The second register stores a round key inputted in every round. The XOR operator XOR-operates the values stored in the first and second registers. The substituting unit substitutes the XOR-operated result according to ARIA substitution algorithm. The diffusing unit diffuses the substitution result of the substituting unit according to ARIA diffusion algorithm in case that it is not a last round. The controlling unit outputs the first control signal for outputting an output of the diffusing unit in case that it is not the last round, and an output of the substituting unit as the intermediate calculation value in case that it is the last round, and outputs an output of the XOR operator as the ARIA encoded/decoded result.

Abstract translation: 提供了ARIA编码/解码的装置和方法以及用于产生其初始密钥的方法，以通过不同种类的四个S盒进行替代操作来减小电路的尺寸。 ARIA编码/解码装置迭代地包括第一寄存器（12），第二寄存器（13），XOR处理器（14），替代单元（15），漫射单元（16）和控制单元 ）。 第一寄存器根据第一控制信号存储输入数据或中间计算值。 第二个寄存器存储每轮输入的一个圆键。 XOR运算符XOR运算存储在第一和第二寄存器中的值。 替代单位根据ARIA替换算法代替XOR运算结果。 扩散单元根据ARIA扩散算法扩散替代单位的替代结果，以防其不是最后一轮。 在不是最后一轮的情况下，控制单元输出用于输出漫射单元的输出的第一控制信号，并且在最后一轮的情况下输出替代单元的输出作为中间计算值，并输出 输出XOR运算符作为ARIA编码/解码结果。

公开(公告)号：KR100576714B1

公开(公告)日：2006-05-03

申请号：KR1020030095373

申请日：2003-12-23

Applicant: 한국전자통신연구원

Inventor： 전용성 ,  박지만 ,  박영수 ,  전성익 ,  정교일

IPC: H04L9/00

CPC classification number: G06F7/584 ,  G06F7/582 ,  H04L9/0662 ,  H04L2209/12

Abstract: 디지털 로직을 이용한 난수 발생 장치 및 방법이 개시되어 있다. 난수 발생 장치는, 내부에 저장된 비트 값들을 순차적으로 이동시키는 쉬프트 레지스터, 상기 쉬프트 레지스터에 저장된 비트 값들을 소정 논리 연산하여 생성한 궤환신호를 생성하는 궤환회로, 쉬프트 레지스터로 입력되는 외부 신호를 생성하는 외부신호 생성회로, 및 궤환신호 및 외부신호를 소정 논리연산하여 쉬프트 레지스터로 출력하는 입력 논리회로를 포함하고, 난수 발생 방법은, 쉬프트 레지스터 내부에 저장된 비트 값들을 순차적으로 이동시키는 단계, 쉬프트 레지스터에 저장된 비트 값들을 소정 논리연산하여 궤환신호를 생성하는 단계, 쉬프트 레지스터로 입력되는 외부 신호를 생성하는 단계, 및 궤환신호 및 외부신호를 소정 논리연산하여 쉬프트 레지스터로 출력하는 단계를 포함한다.

公开(公告)号：KR1020040045152A

公开(公告)日：2004-06-01

申请号：KR1020020073187

申请日：2002-11-22

Applicant: 한국전자통신연구원

Inventor： 김영세 ,  전용성 ,  이상우 ,  이윤경 ,  전성익 ,  박영수

IPC: G06F7/52

Abstract: PURPOSE: A modular multiplying device is provided to successively perform a modular operation by removing the complexity and a delay, and removing or minimizing the delay due to a process inputting data to a modular multiplier from a memory as omitting a Montgomery correction factor calculation process needed during the operation process. CONSTITUTION: A CPU(120) is connected to a system bus(100). The memory(110) inputs/outputs the data needed for the modular multiplication operation. The 2-step registers(101-103) respectively store a multiplier, a multiplicand, and a modulus inputted from the system bus. An operation core(105) performs the modular operation by receiving the data stored in the 2-step registers, outputs a carry-out and a sum-out by dividing a result value, and stores the shift data and a Montgomery correction factor occurred during the operation process. A state register(107) stores/informs the outside of an operation state. A control register(108) receives/stores a control signal of the CPU. A register group(109) stores the partial multiplication during the multiplication operation, and stores/outputs the final result value.

Abstract translation: 目的：提供模块化乘法装置，以通过消除复杂性和延迟，以及消除或最小化由于将数据从存储器输入到模数乘法器的过程所需的延迟，以省略所需的蒙哥马利校正因子计算过程来连续执行模块化操作 在操作过程中。 构成：CPU（120）连接到系统总线（100）。 存储器（110）输入/输出模乘操作所需的数据。 2步寄存器（101-103）分别存储从系统总线输入的乘法器，乘法器和模数。 操作核心（105）通过接收存储在2步寄存器中的数据来执行模块化操作，通过除以结果值来输出进位输出和总和，并存储移位数据和在 操作流程。 状态寄存器（107）存储/通知外部操作状态。 控制寄存器（108）接收/存储CPU的控制信号。 寄存器组（109）在乘法运算期间存储部分乘法，并存储/输出最终结果值。

公开(公告)号：KR1020040032199A

公开(公告)日：2004-04-17

申请号：KR1020020059763

申请日：2002-10-01

Applicant: 한국전자통신연구원

Inventor： 정임영 ,  전용성 ,  전성익 ,  정교일 ,  염헌영

IPC: G06F12/02

CPC classification number: G07F7/1008 ,  G06F11/1471 ,  G06Q20/341 ,  G06Q20/3552 ,  G06Q20/357 ,  Y10S707/99953

Abstract: PURPOSE: A method and a device for storing data on a nonvolatile memory are provided to shorten a response time and lengthen a lifetime of the memory by shortening a delay for storing the data, reducing an access frequency, and uniformly writing to entire memory. CONSTITUTION: Directly after transferring logs of a RAM to a transaction buffer, a transaction completion response is sent(125). In case that a write request to an EEPROM(Electronically Erasable Programmable ROM) is received, it is judged that an address to be updated from the remaining logs is existed on the same page as the page including the address on the EEPROM receiving a write instruction(127). Finding all logs corresponding to the page of the same address as the write request address, contents of the page are updated at once(128). In the case that the corresponding log is not existed, only a part receiving the write request is written(130). When all logs of the transaction are updated, an internal state of a card gets to be the state that the transaction process is terminated(131).

Abstract translation: 目的：提供一种在非易失性存储器上存储数据的方法和装置，通过缩短存储数据的延迟，减少存取频率，并且对整个存储器均匀地写入来缩短响应时间并延长存储器的使用寿命。 构成：将RAM的日志传送到事务缓冲区之后，发送事务完成响应（125）。 在接收到对EEPROM（电可擦除可编程ROM）的写入请求的情况下，判定从与剩余记录更新的地址存在于与包含写入指令的EEPROM上的地址相同的页面上 （127）。 查找与写入请求地址相同的地址对应的所有日志，页面的内容一次更新（128）。 在不存在对应的日志的情况下，仅写入接收写入请求的部分（130）。 当事务的所有日志被更新时，卡的内部状态将成为事务处理终止的状态（131）。