公开(公告)号：WO1992017939A1

公开(公告)日：1992-10-15

申请号：PCT/US1992002740

申请日：1992-04-03

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  VINCELETTE, Scott

IPC: H03K05/24

CPC classification number: H03K5/2481 ,  H03K3/35613 ,  H03K5/249

Abstract: An all CMOS voltage comparator circuit which incorporates a strobed latch. A strobe signal precharges the entire circuit to a known state which is independent of the input voltages and in which substantially no static current is drawn. Under static conditions after the circuit has been strobed, the source-coupled pair (52, 54) is virtually disconnected from the supply voltage(s) and draws almost no current, as well. When the circuit is strobed, a source-coupled FET pair (52, 54) amplifies the differential input signal, with positive feedback provided through a pair of cross-coupled PMOS load transistors (36, 38) as well as cross-coupled NMOS cascode transistors (46, 48). The source-coupled pair feeds a pair of output buffers (62-68) or drivers, whose FETS are sized such that a 'low' voltage level is generated on both outputs until the source-coupled pair resolves the input voltage difference (i.e., the differential input voltage exceeds the switching threshold). At that time, the outputs become complementary digital levels and are usable.

公开(公告)号：WO1991005422A1

公开(公告)日：1991-04-18

申请号：PCT/US1990005579

申请日：1990-10-01

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  DEVITO, Lawrence, M.

IPC: H04L07/033

CPC classification number: H04L7/033 ,  H03L7/091

Abstract: A phase-detector circuit for a phase-locked loop clock recovery system detects the phase difference between an information signal and a clock signal and produces a phase error signal representative of the phase difference. The phase detector includes four latches, serially interconnected, with the first latch (70) receiving the information signal and each subsequent latch receiving the data outpout of the previous latch. The latches are enabled, in an alternating pattern, by the high-level and low-level portions of the clock signal. A first exclusive-OR (XOR) (20) gate receives a delayed information signal and the data output of the second latch (72). A second XOR gate (22) receives the data output of the second latch (72) and the data output of the third latch (74). A third XOR (24) gate receives the data output of the third latch (74) and the data output of the fourth latch (76). A control element, responsive to the outputs of the first, second, third XOR gates, controls the voltage across a capacitor, which has at least one electrode serving as an output terminal for producing the phase error signal. The phase-locked loop clock recovery system provides zero static phase offset and minimal phase jitter in response to data density variations in the information signal.

公开(公告)号：WO1991005350A1

公开(公告)日：1991-04-18

申请号：PCT/US1990005474

申请日：1990-09-26

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MANGELSDORF, Christopher, W. ,  ROBERTSON, David, H. ,  MERCER, Douglas, A. ,  REAL, Peter

IPC: G11C27/02

CPC classification number: G11C27/028

Abstract: A sample-and-hold amplifier in which the held signal is represented as a voltage across a capacitor, but all other signals are represented as currents. At a summing node, the input current and a feedback current are summed to produce a difference current. In the tracking mode, this difference current flows through a closed hold switch onto the input of an integrator. The integrator accumulates the difference current onto the hold capacitor, where it becomes the hold voltage. This hold voltage is converted into a feedback current by a first transconductance amplifier, to provide the negative feedback to the summing node. The hold voltage, which need not equal the input signal, is also applied to the input of a second transconductance amplifier, which provides an output current. The ratio of the two transconductance gains determines the gain accuracy and linearity of the current output. When the hold switch is opened, there is no longer a current path into the hold capacitor, and the output current remains where it was at the moment the switch was opened.

Abstract translation: 一个采样和保持放大器，其中保持的信号被表示为电容器两端的电压，但所有其他信号都表示为电流。 在求和节点，将输入电流和反馈电流相加以产生差分电流。 在跟踪模式下，该差分电流通过闭合保持开关流过积分器的输入。 积分器将差分电流累积到保持电容上，在此保持电容成为保持电压。 该保持电压由第一跨导放大器转换成反馈电流，以向求和节点提供负反馈。 不需要等于输入信号的保持电压也被施加到提供输出电流的第二跨导放大器的输入端。 两个跨导增益的比值决定了电流输出的增益精度和线性度。 当保持开关打开时，不再有保持电容器的电流通路，输出电流保持在开关断开的位置。

公开(公告)号：WO1991005301A1

公开(公告)日：1991-04-18

申请号：PCT/US1990005473

申请日：1990-09-26

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  REAL, Peter ,  ROBERTSON, David, H. ,  TEWKSBURY, Theodore ,  MANGELSDORF, Christopher, W.

IPC: G05F03/22

CPC classification number: H03K17/14 ,  G05F3/227

Abstract: A reference voltage distribution system for use on an integrated circuit to distribute, from a reference voltage input, to remote locations on the chip, precise images of the reference voltage. The system comprises (1) a reference buffer located proximate a reference input connection and (2) a plurality of remote generator blocks, one located at each of the remotely-located sub-blocks or circuits requiring an image of the reference voltage. The reference buffer generates from the reference voltage a number of precision currents, each proportional to the reference voltage. These precision currents are routed to the remote generator blocks. Each remote generator block converts its precision current into a precision reference voltage for local use. These latter reference voltages may be the same as or different from the reference voltage supplied to chip itself.

公开(公告)号：WO1991004576A1

公开(公告)日：1991-04-04

申请号：PCT/US1990005296

申请日：1990-09-18

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  WURCER, Scott

IPC: H01L27/02

CPC classification number: H03F3/45376 ,  H01L27/0211

Abstract: In an FET differential input, preferably using a quad set of devices according to the teaching of U.S. Patent 3,729,666, the channel of each transistor is formed in a piecewise manner, of multiple segments. Each channel segment is associated with a corresponding drain segment (i.e., these are multi-drain devices). Each drain segment is connected in series with a thin-film resistor. The channel area associated with each drain segment can be selectively removed from the circuit by cutting the connected resistor with a laser. The device's channel area (and its effective width to length ratio, Z/L) is thereby alterable. The thin film resistors are cut as the offset is measured, until an acceptably low (effectively zero) offset is obtained. This trimming operation can be performed at room temperature, and yields not only a near zero offset voltage, but also near zero drift. CMRR, further, will be maximized. Neither operating current ratio nor drain voltage need be, or is, changed.

公开(公告)号：WO1990003034A1

公开(公告)日：1990-03-22

申请号：PCT/US1989003919

申请日：1989-09-11

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MILLER, Gerald ,  O'CONNOR, Christopher

IPC: G11C27/02

CPC classification number: H03F1/303 ,  G11C27/026

Abstract: A sample hold amplifier in which the circuit output tracks the voltage input, and, in response to a command signal, samples and accurately holds the sampled input voltage at the amplifier output. In this SHA, both the input and the output are buffered, and the input voltage is sampled not only across a primary ''hold'' capacitor (18), but also across a secondary ''hold'' capacitor (20) at the output of the amplifier, so as to reduce voltage excursions at the output of the circuit due to buffer offsets. The input and output buffers introduce complementary, equal magnitude offset voltages which, together with a unique feedback arrangement to control charging of the output amplifier capacitor, enables auto-zeroing of internal amplifier offset errors.

Abstract translation: 采样保持放大器，其中电路输出跟踪电压输入，并且响应于命令信号采样并且将放大器输出处的采样输入电压精确地保持。 在该SHA中，输入和输出都被缓冲，并且输入电压不仅在初级保持电容器18上被采样，而且还跨越次级“保持”电容器20在 放大器的输出，以便减少由于缓冲器偏移导致的电路输出处的电压偏移。 输入和输出缓冲器引入互补的等幅度补偿电压，连同独特的反馈装置来控制输出放大器电容器的充电，可以自动归零内部放大器偏移误差。

公开(公告)号：WO1989011758A1

公开(公告)日：1989-11-30

申请号：PCT/US1989000945

申请日：1989-03-09

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MANGELSDORF, Christopher, W.

IPC: H03M01/36

CPC classification number: H03M1/1071 ,  H03M1/361

Abstract: In a parallel (or "flash") type analog-to-digital converter (ADC), a decoding technique and apparatus. First, the output of every comparator is examined relative to its nearest neighbors. If, for comparator "n", the outputs of "neighboring" comparators "n + 1" and "n - 1" both are in a different state than the output of comparator "n", the output state of comparator "n" is reversed. That is, each group of three adjacent comparators (n-1, n and n+1) is examined and the output of the "center" comparator (i.e., comparator "n") is corrected. Second, the zeroes-to-ones transition point is found in the thus-corrected outputs. Once the transition point is found, a conventional encoding produces a digital output word. Circuitry is provided for the efficient implementation of the method and for performing the method in an equivalent single step.

公开(公告)号：WO1989004949A2

公开(公告)日：1989-06-01

申请号：PCT/US1988003668

申请日：1988-10-19

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  DEVITO, Lawrence, M. ,  BROKAW, A., Paul

IPC: G01D05/22

CPC classification number: G01D5/2266 ,  G01D5/2216 ,  G01D5/2291 ,  G06G7/161

Abstract: A monolithic interface circuit for use with a linear variable differential transformer (LVDT) position transducer. The interface circuit includes a drive circuit for providing an excitation signal of selectable frequency and amplitude to the LVDT primary winding. The interface circuit further includes a decoder responsive to signals induced in the LVDT secondary windings for computing the position p of the LVDT core as a solution to the equation p= K(A-B)/(A+B), where A and B represent the signals induced in the primary winding and K is a constant scale factor. The decoder includes circuitry for rectifying and filtering the secondary signals, a charge balance loop responsive to the detected signals for providing a binary signal having a duty cycle representative of B/(A+B), and an output circuit responsive to the binary signal for providing the position output. The decoder provides excellent scale factor stability and linearity and is relatively insensitive to variations in primary drive amplitude.

Abstract translation: 用于线性可变差动变压器（LVDT）位置传感器的单片接口电路。 接口电路包括用于向LVDT初级绕组提供可选频率和幅度的激励信号的驱动电路。 接口电路还包括响应于在LVDT次级绕组中感应的信号的解码器，用于计算LVDT磁芯的位置p作为等式p = K（AB）/（A + B）的解，其中A和B表示 在初级绕组中感应的信号和K是恒定比例因子。 解码器包括用于对二次信号进行整流和滤波的电路，响应于检测信号的电荷平衡环路，用于提供具有表示B /（A + B）的占空比的二进制信号，以及响应二进制信号的输出电路， 提供位置输出。 解码器提供优异的比例因子稳定性和线性度，并且对初级驱动幅度的变化相对不敏感。

公开(公告)号：WO1989002082A1

公开(公告)日：1989-03-09

申请号：PCT/US1988002928

申请日：1988-08-24

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  WEB, Spencer, L.

IPC: G01R33/04

CPC classification number: G01R33/04

Abstract: A magnetometer having only a single coil winding for sensing the magnetic field along a single axis. Functionally, the invention comprises an oscillator, and means for measuring the duty cycle thereof. The oscillator uses a saturating inductor which also serves as the magnetic-field-sensing element. The inductor is driven with a positive voltage and when the current through the inductor exceeds a value which indicates that the core is saturated, the driving voltage switches to an equal-magnitude negative value. This negative drive is maintained until the current again indicates the core to be saturated, at which point the driving voltage switches back to the positive value. With no externally applied field, the inductor current averages to a zero value and the duty cycle of the driving voltage is fifty percent. An externally applied field helps the core saturate in one direction and hinders it in the other, resulting in a change in average inductor current and drive duty cycle.

公开(公告)号：WO1998016040A1

公开(公告)日：1998-04-16

申请号：PCT/US1997017934

申请日：1997-10-03

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  ADAMS, Robert, W.

IPC: H04L25/49

CPC classification number: H04L25/4904 ,  H04L7/0331

Abstract: A circuit for decoding an input signal includes a measurement circuit having an input to receive a timing clock signal that is asynchronous with clocking of the input signal, to measure duration of a plurality of pulses received on the input signal in relation to frequency of the timing clock signal and a decode circuit to decode the input signal into digital data. In one embodiment, the circuit may include a servo mechanism for generating the timing clock signal to have a frequency that varies in response to variations in frequency of clocking of data on the input signal. The servo mechanism may include a digitally controlled oscillator and a feedback circuit, to control the digital frequency of the digitally controlled oscillator in response to variation of clocking of data on the input signal. The invention permits use of all digital components for decoding digital audio data encoding using biphase-mark encoded data according to the SPDIF or AES/EBU standards.

Abstract translation: 用于对输入信号进行解码的电路包括测量电路，其具有用于接收与输入信号的时钟异步的定时时钟信号的输入，以测量相对于定时频率在输入信号上接收的多个脉冲的持续时间 时钟信号和解码电路，将输入信号解码为数字数据。 在一个实施例中，电路可以包括用于产生定时时钟信号以使得响应于输入信号上的数据的时钟频率变化而变化的频率的伺服机构。 伺服机构可以包括数字控制振荡器和反馈电路，以响应于输入信号上的数据的时钟变化来控制数字控制振荡器的数字频率。 本发明允许使用所有数字组件来根据SPDIF或AES / EBU标准对使用双相标记编码数据的数字音频数据编码进行解码。