ANALOG-TO-DIGITAL CONVERTER EMPLOYING A PIPELINED MULTI-STAGE ARCHITECTURE
    1.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER EMPLOYING A PIPELINED MULTI-STAGE ARCHITECTURE 审中-公开
    使用管道多级架构的模拟数字转换器

    公开(公告)号:WO1991005409A2

    公开(公告)日:1991-04-18

    申请号:PCT/US1990005472

    申请日:1990-09-26

    CPC classification number: H03M1/129 H03M1/168

    Abstract: A pipelined multi-stage ADC in which residue signals are passed between stages as currents. All sample-and-hold circuits are designed to be current-in/current-out structures; all but one also provide a voltage output. A voltage representation of the analog signal is provided as input to the flash converter within the quantization loop of each stage, allowing implementation of a conventional voltage comparator architecture in the flash converter. An extra comparator is added to the flash converter and an extra segment is included in the DAC of each stage. Inputs above full scale and below zero can be converted and generate output codes. Whenever the input goes above full scale or below zero, an out-of-range bit is set and the digital outputs are set to all ones or all zeroes, respectively. The combination of out-of-range bit and digital codes tell whether overranging or underranging occurred.

    CURRENT MODE SAMPLE-AND-HOLD AMPLIFIER
    2.
    发明申请
    CURRENT MODE SAMPLE-AND-HOLD AMPLIFIER 审中-公开
    电流模式采样和保持放大器

    公开(公告)号:WO1991005350A1

    公开(公告)日:1991-04-18

    申请号:PCT/US1990005474

    申请日:1990-09-26

    CPC classification number: G11C27/028

    Abstract: A sample-and-hold amplifier in which the held signal is represented as a voltage across a capacitor, but all other signals are represented as currents. At a summing node, the input current and a feedback current are summed to produce a difference current. In the tracking mode, this difference current flows through a closed hold switch onto the input of an integrator. The integrator accumulates the difference current onto the hold capacitor, where it becomes the hold voltage. This hold voltage is converted into a feedback current by a first transconductance amplifier, to provide the negative feedback to the summing node. The hold voltage, which need not equal the input signal, is also applied to the input of a second transconductance amplifier, which provides an output current. The ratio of the two transconductance gains determines the gain accuracy and linearity of the current output. When the hold switch is opened, there is no longer a current path into the hold capacitor, and the output current remains where it was at the moment the switch was opened.

    Abstract translation: 一个采样和保持放大器,其中保持的信号被表示为电容器两端的电压,但所有其他信号都表示为电流。 在求和节点,将输入电流和反馈电流相加以产生差分电流。 在跟踪模式下,该差分电流通过闭合保持开关流过积分器的输入。 积分器将差分电流累积到保持电容上,在此保持电容成为保持电压。 该保持电压由第一跨导放大器转换成反馈电流,以向求和节点提供负反馈。 不需要等于输入信号的保持电压也被施加到提供输出电流的第二跨导放大器的输入端。 两个跨导增益的比值决定了电流输出的增益精度和线性度。 当保持开关打开时,不再有保持电容器的电流通路,输出电流保持在开关断开的位置。

    REFERENCE VOLTAGE DISTRIBUTION SYSTEM
    3.
    发明申请
    REFERENCE VOLTAGE DISTRIBUTION SYSTEM 审中-公开
    参考电压分配系统

    公开(公告)号:WO1991005301A1

    公开(公告)日:1991-04-18

    申请号:PCT/US1990005473

    申请日:1990-09-26

    CPC classification number: H03K17/14 G05F3/227

    Abstract: A reference voltage distribution system for use on an integrated circuit to distribute, from a reference voltage input, to remote locations on the chip, precise images of the reference voltage. The system comprises (1) a reference buffer located proximate a reference input connection and (2) a plurality of remote generator blocks, one located at each of the remotely-located sub-blocks or circuits requiring an image of the reference voltage. The reference buffer generates from the reference voltage a number of precision currents, each proportional to the reference voltage. These precision currents are routed to the remote generator blocks. Each remote generator block converts its precision current into a precision reference voltage for local use. These latter reference voltages may be the same as or different from the reference voltage supplied to chip itself.

    RECTIFIER AND INTEGRATOR CIRCUIT FOR DISK DRIVE SERVO SYSTEM
    4.
    发明申请
    RECTIFIER AND INTEGRATOR CIRCUIT FOR DISK DRIVE SERVO SYSTEM 审中-公开
    用于磁盘驱动器伺服系统的整流器和集成电路

    公开(公告)号:WO1996008816A1

    公开(公告)日:1996-03-21

    申请号:PCT/US1995011535

    申请日:1995-09-12

    CPC classification number: G11B5/59655

    Abstract: A servo system for controlling the position of a read/write head in a disk drive is provided. The servo system includes two input terminals for sequentially receiving a plurality of input signal AC voltage bursts of a burst pattern, wherein the input signal bursts include positional information of the head. Demodulation circuitry, coupled to the input terminals, sequentially demodulates each input signal burst and provides a demodulated signal for each burst. The demodulation circuitry includes translation circuitry, coupled to the input, for sequentially translating each input voltage burst to a translated current. A rectifier circuit, coupled to the translation circuitry, including an absolute value circuit and a current mirror circuit, sequentially rectifies each translated current and produces a driving signal. An integrator, coupled to the rectifier circuit, sequentially integrates each driving signal. The integrator includes an integration capacitor which is sequentially charged by each driving signal. In the preferred embodiment, the current mirror circuit includes an operational amplifier and a gain circuit. Also in the prefered embodiment, the voltage to current translation circuit includes a folded cascode circuit arrangement of a plurality of CMOS transistors.

    Abstract translation: 提供了一种用于控制磁盘驱动器中读/写磁头的位置的伺服系统。 伺服系统包括两个输入端子,用于顺序地接收突发模式的多个输入信号AC电压脉冲串,其中输入信号脉冲串包括磁头的位置信息。 耦合到输入端的解调电路顺序地解调每个输入信号脉冲串,并为每个脉冲串提供解调信号。 解调电路包括耦合到输入的平移电路,用于将每个输入电压脉冲串顺序地转换成转换的电流。 耦合到包括绝对值电路和电流镜电路的平移电路的整流器电路顺序地对每个转换的电流进行整流并产生驱动信号。 耦合到整流电路的积分器顺序地对每个驱动信号进行积分。 积分器包括由每个驱动信号依次充电的积分电容器。 在优选实施例中,电流镜电路包括运算放大器和增益电路。 同样在优选实施例中,电压 - 电流转换电路包括多个CMOS晶体管的折叠共源共栅电路装置。

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