Abstract:
A pipelined multi-stage ADC in which residue signals are passed between stages as currents. All sample-and-hold circuits are designed to be current-in/current-out structures; all but one also provide a voltage output. A voltage representation of the analog signal is provided as input to the flash converter within the quantization loop of each stage, allowing implementation of a conventional voltage comparator architecture in the flash converter. An extra comparator is added to the flash converter and an extra segment is included in the DAC of each stage. Inputs above full scale and below zero can be converted and generate output codes. Whenever the input goes above full scale or below zero, an out-of-range bit is set and the digital outputs are set to all ones or all zeroes, respectively. The combination of out-of-range bit and digital codes tell whether overranging or underranging occurred.
Abstract:
A sample-and-hold amplifier in which the held signal is represented as a voltage across a capacitor, but all other signals are represented as currents. At a summing node, the input current and a feedback current are summed to produce a difference current. In the tracking mode, this difference current flows through a closed hold switch onto the input of an integrator. The integrator accumulates the difference current onto the hold capacitor, where it becomes the hold voltage. This hold voltage is converted into a feedback current by a first transconductance amplifier, to provide the negative feedback to the summing node. The hold voltage, which need not equal the input signal, is also applied to the input of a second transconductance amplifier, which provides an output current. The ratio of the two transconductance gains determines the gain accuracy and linearity of the current output. When the hold switch is opened, there is no longer a current path into the hold capacitor, and the output current remains where it was at the moment the switch was opened.
Abstract:
A reference voltage distribution system for use on an integrated circuit to distribute, from a reference voltage input, to remote locations on the chip, precise images of the reference voltage. The system comprises (1) a reference buffer located proximate a reference input connection and (2) a plurality of remote generator blocks, one located at each of the remotely-located sub-blocks or circuits requiring an image of the reference voltage. The reference buffer generates from the reference voltage a number of precision currents, each proportional to the reference voltage. These precision currents are routed to the remote generator blocks. Each remote generator block converts its precision current into a precision reference voltage for local use. These latter reference voltages may be the same as or different from the reference voltage supplied to chip itself.
Abstract:
A servo system for controlling the position of a read/write head in a disk drive is provided. The servo system includes two input terminals for sequentially receiving a plurality of input signal AC voltage bursts of a burst pattern, wherein the input signal bursts include positional information of the head. Demodulation circuitry, coupled to the input terminals, sequentially demodulates each input signal burst and provides a demodulated signal for each burst. The demodulation circuitry includes translation circuitry, coupled to the input, for sequentially translating each input voltage burst to a translated current. A rectifier circuit, coupled to the translation circuitry, including an absolute value circuit and a current mirror circuit, sequentially rectifies each translated current and produces a driving signal. An integrator, coupled to the rectifier circuit, sequentially integrates each driving signal. The integrator includes an integration capacitor which is sequentially charged by each driving signal. In the preferred embodiment, the current mirror circuit includes an operational amplifier and a gain circuit. Also in the prefered embodiment, the voltage to current translation circuit includes a folded cascode circuit arrangement of a plurality of CMOS transistors.
Abstract:
A cascoded current mirror (11) wherein provision is made for connection, such a buffering connection (17, 19), between the cascode portions (23, 13) of the current mirror (11) to provide feedback between such portions.