公开(公告)号：US10769083B2

公开(公告)日：2020-09-08

申请号：US16540477

申请日：2019-08-14

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Vasanth Ranganathan ,  Abhishek R. Appu

IPC: G06F13/16 ,  G06T1/20 ,  G06F13/40 ,  G06F13/42

Abstract: An apparatus to facilitate source synchronous signaling is disclosed. The apparatus includes transfer protocol logic to provide for source synchronous transfer of data within an interconnect fabric, including one or more synchronizers having logic to a transmit data signal and a source clock (clk) signal during the transfer of data.

公开(公告)号：US20200241622A1

公开(公告)日：2020-07-30

申请号：US16782791

申请日：2020-02-05

Applicant: INTEL CORPORATION

Inventor： Abhishek R. Appu ,  Altug Koker ,  Eric J. Hoekstra ,  Kiran C. Veernapu ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Kamal Sinha ,  Balaji Vembu ,  Eric J. Asperheim ,  Sanjeev S. Jahagirdar ,  Joydeep Ray

IPC: G06F1/3225 ,  G06F1/3234

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.

公开(公告)号：US10726792B2

公开(公告)日：2020-07-28

申请号：US15488602

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Arthur J. Runyan ,  Richmond Hicks ,  Nausheen Ansari ,  Narayan Biswal ,  Ya-Ti Peng ,  Abhishek R. Appu ,  Wen-Fu Kao ,  Sang-Hee Lee ,  Joydeep Ray ,  Changliang Wang ,  Satyanarayana Avadhanam ,  Scott Janus ,  Gary Smith ,  Nilesh V. Shah ,  Keith W. Rowe ,  Robert J. Johnston

IPC: G09G3/34 ,  G09G3/36 ,  B60R1/00 ,  G09G5/10 ,  G09G5/14 ,  G09G5/38 ,  G06F3/147 ,  G02B27/01 ,  G09G5/00

Abstract: Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.

公开(公告)号：US10725929B2

公开(公告)日：2020-07-28

申请号：US15483741

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Cristiano J. Ferreira ,  Bo Qiu ,  Ajit Krisshna Nandyal Lakshman ,  Nikhil Talpallikar ,  Deepak Gandiga Shivakumar ,  Brandt M. Guttridge ,  Kim Pallister ,  Frank J. Soqui ,  Anand Srivatsa ,  Travis T. Schluessler ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Altug Koker ,  Jonathan Kennedy

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/10 ,  G06F12/0875 ,  G06F12/0811 ,  G06T1/60 ,  G06F3/06 ,  G06F12/06 ,  G06F12/02 ,  G06F12/109

Abstract: An embodiment of an electronic processing system may include an application processor, system memory communicatively coupled to the application processor, a graphics processor communicatively coupled to the application processor, graphics memory communicatively coupled to the graphics processor, and persistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media. The persistent storage media may include a low latency, high capacity, and byte-addressable nonvolatile memory. The one or more graphics assets may include one or more of a mega-texture and terrain data. Other embodiments are disclosed and claimed.

公开(公告)号：US20200098167A1

公开(公告)日：2020-03-26

申请号：US16456645

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Vasanth Ranganathan ,  Saikat Mandal ,  Saurabh Sharma ,  Vamsee Vardhan Chivukula ,  Karol A. Szerszen ,  Aleksander Olek Neyman ,  Altug Koker ,  Prasoonkumar Surti ,  Abhishek Appu ,  Joydeep Ray ,  Art Hunter ,  Luis F. Cruz Camacho ,  Akshay R. Chada

IPC: G06T15/40 ,  G06T15/00

Abstract: Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.

公开(公告)号：US10599438B2

公开(公告)日：2020-03-24

申请号：US16388444

申请日：2019-04-18

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G06T1/20 ,  G06F9/50 ,  G06F9/48 ,  G06F9/38 ,  G06F9/46 ,  G06F9/52 ,  G06F9/54 ,  G06F15/16 ,  G06F15/76 ,  G06F12/0897 ,  G06F12/0866 ,  G06T1/60

Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.

公开(公告)号：US20200082494A1

公开(公告)日：2020-03-12

申请号：US16572161

申请日：2019-09-16

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Ankur N. Shah ,  Abhishek R. Appu ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall ,  Atsuo Kuwahara ,  Travis T. Schluessler ,  Linda L. Hurd ,  Josh B. Mastronarde ,  Vasanth Ranganathan

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: An embodiment of a graphics apparatus may include a context engine to determine contextual information, a recommendation engine communicatively coupled to the context engine to determine a recommendation based on the contextual information, and a configuration engine communicatively coupled to the recommendation engine to adjust a configuration of a graphics operation based on the recommendation. Other embodiments are disclosed and claimed.

公开(公告)号：US10558254B2

公开(公告)日：2020-02-11

申请号：US15477042

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Eric J. Hoekstra ,  Kiran C. Veernapu ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Kamal Sinha ,  Balaji Vembu ,  Eric J. Asperheim ,  Sanjeev S. Jahagirdar ,  Joydeep Ray

IPC: G06F3/06 ,  G06F1/3225 ,  G06F1/3234

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200042417A1

公开(公告)日：2020-02-06

申请号：US16526069

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Balaji Vembu ,  Josh B. Mastronarde ,  Altug Koker ,  Eric C. Samson ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Vasanth Ranganathan ,  Sanjeev S. Jahagirdar

IPC: G06F11/30 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3296 ,  G05F1/10 ,  G05F1/571 ,  G06F11/32 ,  G06F11/34

Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200020070A1

公开(公告)日：2020-01-16

申请号：US16584076

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Linda L. Hurd ,  Dukhwan Kim ,  Mike B. Macpherson ,  John C. Weast ,  Feng Chen ,  Farshad Akhbari ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman

IPC: G06T1/20 ,  G09G5/36 ,  G06T15/00 ,  G06N3/08 ,  G06N3/063 ,  G06N3/04 ,  G06F9/38 ,  G06F9/30 ,  G06F3/14

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core to perform a mixed precision multi-dimensional matrix multiply and accumulate operation on 8-bit and/or 32 bit signed or unsigned integer elements.