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公开(公告)号：US20180150301A9
公开(公告)日：2018-05-31
申请号：US13898189
申请日：2013-05-20
Applicant: Intel Corporation
Inventor： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
CPC classification number: G06F9/3861 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345
Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
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112.发明授权公开(公告)号：US09971615B2
公开(公告)日：2018-05-15
申请号：US13836628
申请日：2013-03-15
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Stalinselvaraj Jeyasingh , Alain Kagi , Gilbert Neiger , Richard Uhlig , Xiang Zou , Lawrence Smith, III , Scott Rodgers
CPC classification number: G06F9/45533 , G06F9/45558 , G06F2009/45583
Abstract: In one embodiment, a predefined behavior of a virtual machine monitor (VMM) with respect to one or more virtual machines (VMs) is identified, and processor-managed resources associated with the one or more VMs are utilized based on the predefined behavior of the VMM.
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公开(公告)号：US20170351515A1
公开(公告)日：2017-12-07
申请号：US15683331
申请日：2017-08-22
Applicant: Intel Corporation
Inventor： Rebekah Leslie-Hurd , Carlos V. Rozas , Vincent R. Scarlata , Simon P. Johnson , Uday R. Savagaonkar , Barry E. Huntley , Vedvyas Shanbhogue , Ittai Anati , Francis X. Mckeen , Michael A. Goldsmith , Ilya Alexandrovich , Alex Berenzon , Wesley H. Smith , Gilbert Neiger
IPC: G06F9/30 , G06F9/44 , G06F12/0875 , G06F12/084 , G06F12/14
CPC classification number: G06F9/3004 , G06F9/30047 , G06F9/30076 , G06F9/44 , G06F12/084 , G06F12/0875 , G06F12/1483 , G06F2212/452
Abstract: Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes allocating a page in an enclave page cache to a secure enclave. The execution unit is also to execute the second instruction, wherein execution of the second instruction includes confirming the allocation of the page.
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114.发明授权公开(公告)号：US09804870B2
公开(公告)日：2017-10-31
申请号：US13629395
申请日：2012-09-27
Applicant: Intel Corporation
Inventor： Gilbert Neiger , Barry E. Huntley , Ravi L. Sahita , Vedvyas Shanbhogue , Jason W. Brandt
IPC: G06F9/455
CPC classification number: G06F9/45545 , G06F9/455 , G06F9/45533 , G06F9/4555
Abstract: A processing core comprising instruction execution logic circuitry and register space. The register space to be loaded from a VMCS, commensurate with a VM entry, with information indicating whether a service provided by the processing core on behalf of the VMM is enabled. The instruction execution logic to, in response to guest software invoking an instruction: refer to the register space to confirm that the service has been enabled, and, refer to second register space or memory space to fetch input parameters for said service written by said guest software.
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115.发明授权公开(公告)号：US09710401B2
公开(公告)日：2017-07-18
申请号：US14752227
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Carlos V. Rozas , Mona Vij , Rebekah M. Leslie-Hurd , Krystof C. Zmudzinski , Somnath Chakrabarti , Francis X. McKeen , Vincent R. Scarlata , Simon P. Johnson , Ilya Alexandrovich , Gilbert Neiger , Vedvyas Shanbhogue , Ittai Anati
CPC classification number: G06F12/1408 , G06F8/41 , G06F9/30145 , G06F9/45558 , G06F21/53 , G06F21/602 , G06F2009/4557 , G06F2009/45587 , G06F2212/1052
Abstract: A processor includes a decode unit to decode an instruction that is to indicate a page of a protected container memory, and a storage location outside of the protected container memory. An execution unit, in response to the instruction, is to ensure that there are no writable references to the page of the protected container memory while it has a write protected state. The execution unit is to encrypt a copy of the page of the protected container memory. The execution unit is to store the encrypted copy of the page to the storage location outside of the protected container memory, after it has been ensured that there are no writable references. The execution unit is to leave the page of the protected container memory in the write protected state, which is also valid and readable, after the encrypted copy has been stored to the storage location.
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Patent Agency Ranking
公开(公告)号：US09690704B2
公开(公告)日：2017-06-27
申请号：US15091926
申请日：2016-04-06
Applicant: Intel Corporation
Inventor： Francis X. Mckeen , Michael A. Goldsmith , Barry E. Huntley , Simon P. Johnson , Rebekah Leslie-Hurd , Carlos V. Rozas , Uday R. Savagaonkar , Vincent R. Scarlata , Vedvyas Shanbhogue , Wesley H. Smith , Ittai Anati , Ilya Alexandrovich , Alex Berenzon , Gilbert Neiger
IPC: G06F12/00 , G06F12/0804 , G06F9/30 , G06F12/0875 , G06F12/14
CPC classification number: G06F12/0804 , G06F9/30047 , G06F12/0875 , G06F12/1408 , G06F2212/1052 , G06F2212/402
Abstract: Embodiments of an invention for paging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes evicting a first page from an enclave page cache.
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公开(公告)号：US20170177460A1
公开(公告)日：2017-06-22
申请号：US14973238
申请日：2015-12-17
Applicant: Intel Corporation
Inventor： Gilbert Neiger , Andrew V. Anderson , Richard A. Uhlig , David M. Durham , Ronak Singhal , Xiangbin Wu , Sailesh Kottapalli
CPC classification number: G06F11/3466 , G06F3/0604 , G06F3/0644 , G06F3/0673 , G06F11/3024 , G06F13/24
Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.
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公开(公告)号：US20160202976A1
公开(公告)日：2016-07-14
申请号：US15074573
申请日：2016-03-18
Applicant: Intel Corporation
Inventor： Rebekah Leslie-Hurd , Carlos V. Rozas , Vincent R. Scarlata , Simon P. Johnson , Uday R. Savagaonkar , Barry E. Huntley , Vedvyas Shanbhogue , Ittai Anati , Francis X. Mckeen , Michael A. Goldsmith , Ilya Alexandrovich , Alex Berenzon , Wesley H. Smith , Gilbert Neiger
CPC classification number: G06F9/3004 , G06F9/30047 , G06F9/30076 , G06F9/44 , G06F12/084 , G06F12/0875 , G06F12/1483 , G06F2212/452
Abstract: Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes allocating a page in an enclave page cache to a secure enclave. The execution unit is also to execute the second instruction, wherein execution of the second instruction includes confirming the allocation of the page.
Abstract translation: 公开了用于安全飞行器中的存储器管理的发明的实施例。 在一个实施例中，处理器包括指令单元和执行单元。 指令单元接收第一指令和第二指令。 执行单元执行第一指令，其中第一指令的执行包括将飞地页面缓存中的页面分配到安全飞地。 执行单元还执行第二指令，其中第二指令的执行包括确认页的分配。
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公开(公告)号：US09298641B2
公开(公告)日：2016-03-29
申请号：US14867023
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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公开(公告)号：US09298640B2
公开(公告)日：2016-03-29
申请号：US14867018
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard A Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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