公开(公告)号：US09612938B2

公开(公告)日：2017-04-04

申请号：US13895595

申请日：2013-05-16

Applicant: Intel Corporation

Inventor： Frank Binns ,  Matthew C. Merten ,  Mayank Bomb ,  Beeman C. Strong ,  Peter Lachner ,  Jason W. Brandt ,  Itamar Kazachinsky ,  Ofer Levy ,  Md A. Rahman

IPC: G06F7/38 ,  G06F3/00 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F11/3636 ,  G06F11/3024 ,  G06F11/3055 ,  G06F11/3476 ,  G06F11/348 ,  G06F2201/865

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.

公开(公告)号：US20170109192A1

公开(公告)日：2017-04-20

申请号：US15391576

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Mayank Bomb ,  Manohar Castelino ,  Robert Chappell ,  David Durham ,  Barry Huntley ,  Anton Ivanov ,  Madhavan Parthasarathy ,  Scott Rodgers ,  Ravi Sahita ,  Vedvyas Shanbhogue

IPC: G06F9/455 ,  G06F9/48

CPC classification number: G06F9/45558 ,  G06F9/30076 ,  G06F9/45533 ,  G06F9/4555 ,  G06F9/4812 ,  G06F11/07 ,  G06F2009/45583

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

公开(公告)号：US10175990B2

公开(公告)日：2019-01-08

申请号：US13898189

申请日：2013-05-20

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang (Y. K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/38 ,  G06F9/30 ,  G06F9/345

Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

公开(公告)号：US20180150301A9

公开(公告)日：2018-05-31

申请号：US13898189

申请日：2013-05-20

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang (Y.K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345

Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

公开(公告)号：US09753832B2

公开(公告)日：2017-09-05

申请号：US13930501

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Ilya Wagner ,  Matthew C. Merten ,  Frank Binns ,  Christine E. Wang ,  Mayank Bomb ,  Tong Li ,  Thilo Schmitt ,  M D A. Rahman

IPC: G06F9/30 ,  G06F11/34

CPC classification number: G06F11/3466 ,  G06F11/348 ,  G06F2201/81

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for minimizing bandwidth to compress an output stream of an instruction tracing system. For example, the method may include identifying a current instruction in a trace of the IT module as a conditional branch (CB) instruction. The method includes executing one of generating a CB packet including a byte pattern with an indication of outcome of the CB instruction, or adding an indication of the outcome of the CB instruction to the byte pattern of an existing CB packet. The method includes generating a packet when a subsequent instruction in the trace is not the CB instruction. The packet is different from the CB packet. The method also includes adding the packet into a deferred queue when the packet is deferrable. The method further includes outputting the CB packet followed by the deferred packet into a packet log.

公开(公告)号：US10901772B2

公开(公告)日：2021-01-26

申请号：US16380717

申请日：2019-04-10

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Mayank Bomb ,  Manohar Castelino ,  Robert Chappell ,  David Durham ,  Barry Huntley ,  Anton Ivanov ,  Madhavan Parthasarathy ,  Scott Rodgers ,  Ravi Sahita ,  Vedvyas Shanbhogue

IPC: G06F9/455 ,  G06F9/30 ,  G06F9/48 ,  G06F11/07

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

公开(公告)号：US08913740B2

公开(公告)日：2014-12-16

申请号：US13791224

申请日：2013-03-08

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Martin Dixon ,  Srinivas Chennupaty ,  Mayank Bomb ,  Brent Boswell

IPC: H04K1/00 ,  H04L9/00 ,  H04L9/28 ,  H04L9/06

CPC classification number: H04L9/28 ,  G06F9/30007 ,  H04L9/0631 ,  H04L2209/125 ,  H04L2209/24

Abstract: An Advanced Encryption Standard (AES) key generation assist instruction is provided. The AES key generation assist instruction assists in generating round keys used to perform AES encryption and decryption operations. The AES key generation instruction operates independent of the size of the cipher key and performs key generation operations in parallel on four 32-bit words thereby increasing the speed at which the round keys are generated. This instruction is easy to use in software. Hardware implementation of this instruction removes potential threats of software (cache access based) side channel attacks on this part of the AES algorithm.

Abstract translation: 提供了高级加密标准（AES）密钥生成辅助指令。 AES密钥生成辅助指令有助于生成用于执行AES加密和解密操作的循环密钥。 AES密钥生成指令独立于密码密钥的大小，并行执行四个32位字的密钥生成操作，从而增加生成循环密钥的速度。 该指令在软件中易于使用。 该指令的硬件实现可以消除这部分AES算法对软件（基于缓存访问的）侧面信道攻击的潜在威胁。

公开(公告)号：US10296366B2

公开(公告)日：2019-05-21

申请号：US15391576

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Mayank Bomb ,  Manohar Castelino ,  Robert Chappell ,  David Durham ,  Barry Huntley ,  Anton Ivanov ,  Madhavan Parthasarathy ,  Scott Rodgers ,  Ravi Sahita ,  Vedvyas Shanbhogue

IPC: G06F9/455 ,  G06F9/48 ,  G06F11/07

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

公开(公告)号：US09563455B2

公开(公告)日：2017-02-07

申请号：US14064759

申请日：2013-10-28

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Mayank Bomb ,  Manohar Castelino ,  Robert Chappell ,  David Durham ,  Barry Huntley ,  Anton Ivanov ,  Madhavan Parthasarathy ,  Scott Rodgers ,  Ravi Sahita ,  Vedvyas Shanbhogue

IPC: G06F9/455 ,  G06F11/07

CPC classification number: G06F9/45558 ,  G06F9/30076 ,  G06F9/45533 ,  G06F9/4555 ,  G06F9/4812 ,  G06F11/07 ,  G06F2009/45583

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Abstract translation: 公开了用于虚拟化异常的发明的实施例。 在一个实施例中，处理器包括指令硬件，控制逻辑和执行硬件。 指令硬件是接收多个指令，包括进入虚拟机的指令。 控制逻辑是为了响应在虚拟机内发生的特权事件来确定是否生成虚拟化异常。 执行硬件是响应于控制逻辑确定生成虚拟化异常来生成虚拟化异常。