公开(公告)号：US11003444B2

公开(公告)日：2021-05-11

申请号：US16457906

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Shengtian Zhou ,  Mohammad Mejbah ul Alam ,  Justin Gottschlich

IPC: G06F8/75 ,  G06K9/62 ,  G06N5/04 ,  G06F8/72 ,  G06F8/65

Abstract: An apparatus includes a software parser to generate a plurality of abstract syntax trees based on a plurality of software files, the ASTs including subtrees corresponding to a plurality of functions of the software files, a subtree encoder to generate a plurality of code vectors representative of one or more semantic properties of the subtrees, a function identifier to determine a plurality of clusters for the subtrees and assign a cluster identifier and a function label to the subtrees, a tree database to store the subtrees and map the plurality of subtrees to respective ones of cluster identifiers and function names, and a processor to: train a model based on a feature vector and the plurality of clusters stored in the tree database and predict the cluster identifier for the subtrees, based on the trained model, to identify a name of the function.

公开(公告)号：US20210073632A1

公开(公告)日：2021-03-11

申请号：US16951799

申请日：2020-11-18

Applicant: Intel Corporation

Inventor： Roshni G. Iyer ,  Justin Gottschlich ,  Joseph Tarango ,  Jim Baca ,  Niranjan Hasabnis

IPC: G06N3/08 ,  G06N3/04

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for generating code semantics. An example apparatus includes a concept controller to assign semantic labels to repository data to generate a training set, the semantic labels stored in a first semantic graph, the training set including a first code block associated with a first semantic label and a second code block associated with a second semantic label, a concept determiner to generate a first block embedding based on the first code block and a second block embedding based on the second code block, a graph generator to link the first block embedding to the second block embedding to form a second semantic graph, and a graph parser to output at least one of the first code block or the second code block corresponding to a query based on the second semantic graph.

公开(公告)号：US20190325316A1

公开(公告)日：2019-10-24

申请号：US16457133

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Todd A. Anderson ,  Mohammad Mejbah Ul Alam ,  Shengtian Zhou ,  Justin Gottschlich

IPC: G06N3/08 ,  G16H20/30

Abstract: Example apparatus and methods for program synthesis using genetic algorithms are disclosed herein. An example apparatus includes a program length predictor to predict a length of a first program by executing a first neural network model, a program generator to generate a candidate program having a length corresponding to the predicted length, a candidate program analyzer to generate a fitness score for the candidate program by executing a second neural network model and to identify the first candidate program for use in a breeding operation relative a second candidate program based on the fitness score, and a genetic program generator to perform the breeding operation with at least one of the first candidate program or the second candidate program to generate an evolved candidate program.

公开(公告)号：US20190325108A1

公开(公告)日：2019-10-24

申请号：US16456825

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Javier Sebastián Turek ,  Javier Felip Leon ,  Alexander Heinecke ,  Evangelos Georganas ,  Luis Carlos Maria Remis ,  Ignacio Javier Alvarez ,  David Israel Gonzalez Aguirre ,  Shengtian Zhou ,  Justin Gottschlich

IPC: G06F17/50 ,  G06N3/08 ,  G06N3/04

Abstract: Systems and methods for determining a configuration for a microarchitecture are described herein. An example system includes a proposal generator to generate a first candidate configuration of parameters for the microarchitecture, a machine learning model to process the first candidate configuration of parameters to output estimated performance indicators for the microarchitecture, an uncertainty checker to determine whether the estimated performance indicators are reliable, and a performance checker. In response to a determination that the estimated performance indicators are reliable, the performance checker is to determine whether the estimated performance indicators have improved toward a target. Further, if the estimated performance indicators have improved, the performance checker is to store the first candidate configuration of parameters in a memory as a potential solution for a microarchitecture without performing a full simulation on the first candidate configuration of parameters.

公开(公告)号：US20190319977A1

公开(公告)日：2019-10-17

申请号：US16455189

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Justin Gottschlich ,  Rachit Mathur ,  Zheng Zhang

IPC: H04L29/06 ,  G06K9/62

Abstract: Apparatus, systems, methods, and articles of manufacture for fingerprinting and classifying application behaviors using telemetry are disclosed. An example apparatus includes a trace processor to process events in a processor trace to capture application execution behavior; a fingerprint extractor to extract a first fingerprint from the captured application execution behavior and performance monitor information; a fingerprint clusterer to, in a training mode cluster the first fingerprint and the second fingerprint into a cluster of fingerprints to be stored in a fingerprint database with a classification; and a fingerprint classifier to, in a deployed mode, classify a third fingerprint, the fingerprint classifier to trigger a remedial action when the classification is malicious.

公开(公告)号：US20190317880A1

公开(公告)日：2019-10-17

申请号：US16455486

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Adam Herr ,  Sridhar Sharma ,  Mikael Bourges-Sevenier ,  Derek Gerstmann ,  Justin Gottschlich

IPC: G06F11/36 ,  G06N20/00

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed improve runtime performance of software executing on a heterogeneous system. An example apparatus includes a feedback interface to collect a performance characteristic of the heterogeneous system associated with a compiled version of a block of code at a first runtime, the compiled version executed according to a function designating successful execution of the compiled version on the heterogeneous system, the heterogeneous system including a first processing element and a second processing element different than the first processing element; a performance analyzer to determine a performance delta based on the performance characteristic and the function; and a machine learning modeler to, prior to a second runtime, adjust a cost model of the first processing element based on the performance delta, the adjusted cost model to cause a reduction in the performance delta to improve runtime performance of the heterogeneous system.

公开(公告)号：US20190317844A1

公开(公告)日：2019-10-17

申请号：US16453816

申请日：2019-06-26

Applicant: Intel Corporation

Inventor： Justin Gottschlich ,  Mohammad Mejbah Ul Alam ,  Shengtian Zhou

IPC: G06F9/54 ,  G06F16/28 ,  G06N3/04

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to select code data structure types. An example disclosed apparatus includes an application programming interface (API) engine to generate an abstract data structure (ADS) placeholder in a location of a code sample corresponding to a memory operation, and a data structure selector to select a first candidate data structure having a first candidate data structure type, the first candidate data structure to service the memory operation of the ADS placeholder. The example apparatus also includes a workload engine to select a first candidate workload type to be processed by the selected first candidate data structure, and an execution logger to log first code performance metrics during execution of the code sample during a first iteration corresponding to the first candidate data structure type and the first candidate workload type, and log second code performance metrics during execution of the code sample during a second duration corresponding to a second candidate data structure type and the first candidate workload type. The example apparatus also includes a classification engine to select one of the first candidate data structure type or the second candidate data structure type based on a relative ranking of the first and second code performance metrics.

公开(公告)号：US20190317737A1

公开(公告)日：2019-10-17

申请号：US16455259

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Thijs Metsch ,  Mohammad Mejbah Ul Alam ,  Justin Gottschlich

IPC: G06F8/35 ,  G06N20/00

Abstract: Methods, apparatus, systems and articles of manufacture to recommend instruction adaptations to improve compute performance are disclosed. An example apparatus includes a pattern detector to detect an execution pattern from an execution profile provided by a server, the execution profile associated with an instruction stored in an instruction repository. An adaptation identifier is to identify a possible instruction adaptation that may be applied to the instruction associated with the execution pattern. A model processor is to predict, using a machine learning model, an expected performance improvement of the adaptation. A result comparator is to determine whether the expected performance improvement meets an threshold. An instruction editor is to, in response to the result comparator determining that the expected performance improvement meets the threshold, apply the possible instruction adaptation to the instruction in the instruction repository.

公开(公告)号：US20190317455A1

公开(公告)日：2019-10-17

申请号：US16456957

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Javier Felip Leon ,  Javier Sebastian Turek ,  David I. Gonzalez Aguirre ,  Ignacio Javier Alvarez ,  Luis Carlos Maria Remis ,  Justin Gottschlich

IPC: G05B13/02 ,  G05B13/04 ,  G06N3/08 ,  G06N20/00

Abstract: Apparatus, systems, articles of manufacture, and methods to generate acceptability criteria for autonomous systems plans are disclosed. An example apparatus includes a data compiler to compile data generated by the autonomous system into an autonomous system task dataset, a data encoder to encode the dataset for input into a rule distillation neural network architecture, a model trainer to train the rule distillation neural network architecture, an adaptor to adapt the trained rule distillation neural network architecture to a new input data domain using the autonomous system task dataset, a verifier to generate formally verified acceptability criteria, and an inferer to evaluate a control command, the evaluation resulting in an acceptance or rejection of the command.

公开(公告)号：US20190147162A1

公开(公告)日：2019-05-16

申请号：US16226137

申请日：2018-12-19

Applicant: Intel Corporation

Inventor： Mohammad Mejbah Ul Alam ,  Justin Gottschlich ,  Shengtian Zhou

IPC: G06F21/56 ,  G06F21/55 ,  G06N3/08

Abstract: Methods, apparatus, systems and articles of manufacture to identify a side-channel attack are disclosed. An example apparatus includes a vector-to-neuron processor to map an event vector to a neuron of a trained self-organizing map; a buffer processor to identify a task pair based on the neuron and an adjacent neuron of the neuron; a buffer to store data corresponding to the identified task pair; an attack identifier to, when information stored in the buffer corresponds to more than a threshold number of task pairs corresponding to the identified task pair, identify a malware attack; and a mitigation technique selector to select a technique for mitigating the malware attack