公开(公告)号：US20230325246A1

公开(公告)日：2023-10-12

申请号：US18326773

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  John J. Browne ,  Amruta Misra ,  Chris M. MacNamara

IPC: G06F9/50 ,  H04L12/14

CPC classification number: G06F9/5033 ,  G06F9/5044 ,  H04L12/1432

Abstract: A platform includes a plurality of hardware blocks to provide respective functionality for use in execution of an application. A subset of the plurality of hardware blocks are deactivated and unavailable for use in the execution of the application at the start of the execution of the application. A hardware profile modification block of the platform identifies receives telemetry data generated by a set of sensors and dynamically activates at least a particular one of the subset of hardware blocks based on the physical characteristics, where following activation of the particular hardware block, the execution of the application continues and uses the particular hardware block.

公开(公告)号：US20230281113A1

公开(公告)日：2023-09-07

申请号：US18131980

申请日：2023-04-07

Applicant: INTEL CORPORATION

Inventor： Karthik Kumar ,  Francesc Guim Bernat ,  Ramamurthy Krithivas

IPC: G06F12/02

CPC classification number: G06F12/023

Abstract: Techniques for adaptive memory metadata allocation. A processor may determine a first memory region of a plurality of memory regions in a memory pool coupled to the processor via an interface. The processor may modify a metadata of the first memory region from a first configuration to a second configuration, where the first configuration is associated with a first number of error correction code (ECC) bits and the second configuration is associated with a second number of ECC bits.

公开(公告)号：US20230205604A1

公开(公告)日：2023-06-29

申请号：US18069700

申请日：2022-12-21

Applicant: INTEL CORPORATION

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Susanne M. Balle ,  Ignacio Astilleros Diez ,  Timothy Verrall ,  Ned M. Smith

IPC: G06F9/50 ,  G06F9/48

CPC classification number: G06F9/5088 ,  G06F9/4856 ,  G06F9/4881 ,  G06F9/5072 ,  G06F2209/484

Abstract: Technologies for providing efficient migration of services include a server device. The server device includes compute engine circuitry to execute a set of services on behalf of a terminal device and migration accelerator circuitry. The migration accelerator circuitry is to determine whether execution of the services is to be migrated from an edge station in which the present server device is located to a second edge station in which a second server device is located, determine a prioritization of the services executed by the server device, and send, in response to a determination that the services are to be migrated and as a function of the determined prioritization, data utilized by each service to the second server device of the second edge station to migrate the services. Other embodiments are also described and claimed.

公开(公告)号：US20230195597A1

公开(公告)日：2023-06-22

申请号：US17556044

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Mateo Guzman ,  Francesc Guim Bernat ,  Karthik Kumar ,  Marcos Carranza ,  Cesar Martinez-Spessot ,  Rajesh Poornachandran ,  Kshitij Arun Doshi

IPC: G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3656 ,  G06F11/3664 ,  G06F11/366

Abstract: An apparatus to facilitate matchmaking-based enhanced debugging for microservices architectures is disclosed. The apparatus includes one or more processors to: detect, by an anomaly detector in a sidecar of a microservice hosted by a container, an anomaly in telemetry data generated by the microservice, the microservice hosted in a container executed by the processor and part of a service of an application; enable, by an enhanced debug and trace component of the sidecar, a debug mode in the microservice, the debug mode based on a type of the anomaly; collect, by the enhanced debug and trace component, a target set of data points generated by the microservice; and process, by the enhanced debug and trace component, the target set of data points with a matchmaking process to generate a timestamp and a tag for a context for each data point of the target set of data points.

公开(公告)号：US20230022620A1

公开(公告)日：2023-01-26

申请号：US17875672

申请日：2022-07-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Patrick Bohan ,  Kshitij Arun Doshi ,  Brinda Ganesh ,  Andrew J. Herdrich ,  Monica Kenguva ,  Karthik Kumar ,  Patrick G. Kutch ,  Felipe Pastor Beneyto ,  Rashmin Patel ,  Suraj Prabhakaran ,  Ned M. Smith ,  Petar Torre ,  Alexander Vul

IPC: H04L67/148 ,  H04L47/70 ,  H04L43/0811 ,  H04W4/40 ,  H04L67/10 ,  H04W4/70 ,  H04L41/5019 ,  H04L67/00 ,  G06F9/48

Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QoS pre-allocation; and automatic QoS migration across edge computing nodes. In a specific example, a technique for service migration includes: identifying a service operated with computing resources in an edge computing system, involving computing capabilities for a connected edge device with an identified service level; identifying a mobility condition for the service, based on a change in network connectivity with the connected edge device; and performing a migration of the service to another edge computing system based on the identified mobility condition, to enable the service to be continued at the second edge computing apparatus to provide computing capabilities for the connected edge device with the identified service level.

公开(公告)号：US20220263891A1

公开(公告)日：2022-08-18

申请号：US17688695

申请日：2022-03-07

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Ned Smith ,  Thomas Willhalm ,  Karthik Kumar ,  Timothy Verrall

IPC: H04L67/1008 ,  H04L67/1021 ,  H04L67/10 ,  H04L67/00 ,  H04L67/59 ,  H04L67/61 ,  H04L67/63

Abstract: Technologies for providing selective offload of execution of an application to the edge include a device that includes circuitry to determine whether a section of an application to be executed by the device is available to be offloaded. Additionally, the circuitry is to determine one or more characteristics of an edge resource available to execute the section. Further, the circuitry is to determine, as a function of the one or more characteristics and a target performance objective associated with the section, whether to offload the section to the edge resource and offload, in response to a determination to offload the section, the section to the edge resource.

公开(公告)号：US11412052B2

公开(公告)日：2022-08-09

申请号：US16235137

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Patrick Bohan ,  Kshitij Arun Doshi ,  Brinda Ganesh ,  Andrew J. Herdrich ,  Monica Kenguva ,  Karthik Kumar ,  Patrick G Kutch ,  Felipe Pastor Beneyto ,  Rashmin Patel ,  Suraj Prabhakaran ,  Ned M. Smith ,  Petar Torre ,  Alexander Vul

IPC: H04L67/148 ,  H04L43/0811 ,  H04L67/10 ,  H04L41/5019 ,  H04L67/00 ,  H04L41/5003 ,  H04L47/70 ,  H04W4/40 ,  H04W4/70 ,  G06F9/48

Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QoS pre-allocation; and automatic QoS migration across edge computing nodes. In a specific example, a technique for service migration includes: identifying a service operated with computing resources in an edge computing system, involving computing capabilities for a connected edge device with an identified service level; identifying a mobility condition for the service, based on a change in network connectivity with the connected edge device; and performing a migration of the service to another edge computing system based on the identified mobility condition, to enable the service to be continued at the second edge computing apparatus to provide computing capabilities for the connected edge device with the identified service level.

公开(公告)号：US11366782B2

公开(公告)日：2022-06-21

申请号：US17363867

申请日：2021-06-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Mustafa Hajeer

IPC: G06F15/173 ,  H04L67/1097 ,  G06F15/167 ,  H04L9/40

Abstract: An apparatus is described. The apparatus includes logic circuitry embedded in at least one of a memory controller, network interface and peripheral control hub to process a function as a service (FaaS) function call embedded in a request. The request is formatted according to a protocol. The protocol allows a remote computing system to access a memory that is coupled to the memory controller without invoking processing cores of a local computing system that the memory controller is a component of.

公开(公告)号：US20220121556A1

公开(公告)日：2022-04-21

申请号：US17561516

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Sunil Cheruvu ,  Tushar Gohad ,  Karthik Kumar ,  Ned M. Smith

IPC: G06F11/36

Abstract: Systems, methods, articles of manufacture, and apparatus for end-to-end hardware tracing in an Edge network are disclosed. An example compute device includes at least one memory, instructions in the compute device, and processing circuitry to execute the instructions to, in response to receiving detecting an object having a global group identifier, generate monitoring data corresponding to a respective process executing on the compute device, the monitoring data including a process identifier, index the monitoring data having the process identifier to the corresponding global group identifier, synchronize a time stamp of the monitoring data to a network time protocol corresponding to the global group identifier, and transmit the indexed and synchronized monitoring data as tracing data in to the a tracing datastore.

公开(公告)号：US20220091782A1

公开(公告)日：2022-03-24

申请号：US17544091

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar

IPC: G06F3/06

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to persistent media, and manage an endurance of the persistent media based on one or more endurance hints from an external source. Other embodiments are disclosed and claimed.