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    Methods and apparatus to conditionally activate a big core in a computing system
    1.
    发明授权
    Methods and apparatus to conditionally activate a big core in a computing system 有权

    公开(公告)号：US12217175B2

    公开(公告)日：2025-02-04

    申请号：US17560025

    申请日：2021-12-22

    Applicant: Intel Corporation

    Inventor： Rajesh Poornachandran ,  Vincent Zimmer

    IPC: G06F9/46 ,  G06F9/38 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F21/54 ,  G06N3/042 ,  G06N3/063 ,  G06N3/08

    Abstract: Methods, apparatus, and articles of manufacture to conditionally activate a big core in a computing system are disclosed. An example apparatus including instructions stored in the apparatus; and processor circuitry to execute the instructions to: in response to a request to operate two or more processing devices as a single processing device, determine whether the two or more processing devices are available and capable of executing instructions according to the request; when the two or more processing devices are available and capable: split the instructions into first sub-instructions and second sub-instructions; provide (a) the first sub-instructions to a first processing device of the two or more processing devices and (b) the second sub-instructions to a second processing device of the two or more processing devices; and generate an output by combining a first output of the first processing device and a second output of the second processing device.

    Secure application communications through sidecars
    4.
    发明授权
    Secure application communications through sidecars 有权

    公开(公告)号：US12047357B2

    公开(公告)日：2024-07-23

    申请号：US17556671

    申请日：2021-12-20

    Applicant: Intel Corporation

    Inventor： Cesar Martinez-Spessot ,  Marcos Carranza ,  Lakshmi Talluru ,  Mateo Guzman ,  Francesc Guim Bernat ,  Karthik Kumar ,  Rajesh Poornachandran ,  Kshitij Arun Doshi

    IPC: H04L9/40 ,  G06F9/54

    CPC classification number: H04L63/0428 ,  G06F9/547

    Abstract: Embodiments described herein are generally directed to a transparent and adaptable mechanism for performing secure application communications through sidecars. In an example, a set of security features is discovered by a first sidecar of a first microservice of multiple microservices of an application. The set of security features are associated with a device of multiple devices of a set of one or more host systems on which the first microservice is running. Information regarding the set of discovered security features is made available to the other microservices by the first sidecar by sharing the information with a discovery service accessible to all of the microservices. A configuration of a communication channel through which a message is to be transmitted from a second microservice to the first microservice is determined by a second sidecar of the second microservice by issuing a request to the discovery service regarding the first microservice.

    ROOTS OF TRUST IN INTELLECTUAL PROPERTY (IP) BLOCKS IN A SYSTEM ON A CHIP (SOC)
    5.
    发明公开
    ROOTS OF TRUST IN INTELLECTUAL PROPERTY (IP) BLOCKS IN A SYSTEM ON A CHIP (SOC) 审中-公开

    公开(公告)号：US20240195635A1

    公开(公告)日：2024-06-13

    申请号：US18064546

    申请日：2022-12-12

    Applicant: Intel Corporation

    Inventor： Kshitij Doshi ,  Ned M. Smith ,  Rajesh Poornachandran ,  Sunil K. Cheruvu ,  David W. Palmer

    IPC: H04L9/32 ,  H04L9/08

    CPC classification number: H04L9/3247 ,  H04L9/0825 ,  H04L9/0869

    Abstract: The technology described herein includes a plurality of intellectual property (IP) blocks; and a host IP block, the host IP block including a primary root of trust (RoT) IP block (PRIB) coupled to the plurality of IP blocks, to receive a request from a computing system to establish a secure communications session with a selected one of a plurality of intellectual property (IP) blocks, authenticate and attest the computing system, sign evidence of the PRIB with a PRIB key, send the signed evidence of the PRIB to the computing system, and establish the secure communications session between the computing system and the selected IP block if the PRIB is trusted by the computing system based at least in part on the signed evidence of the PRIB.

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