中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

165 records (took 0.025 seconds)

    FREQUENCY AGILE TDMA COMMUNICATIONS SYSTEM
    111.
    发明专利
    FREQUENCY AGILE TDMA COMMUNICATIONS SYSTEM 未知

    公开(公告)号：AU8747491A

    公开(公告)日：1992-04-28

    申请号：AU8747491

    申请日：1991-09-25

    Applicant: MOTOROLA INC

    Inventor： FREEBURG THOMAS A ,  GERHARDT WILLY ,  LEY JOHN

    IPC: H04J3/00 ,  H04B7/26 ,  H04J3/16 ,  H04J4/00

    Abstract: An intelligent communcations node is capable of dynamically selecting frequency and time slot assignments for communications with remote communication devices having different communication protocols including different available frequencies and time slots in a TDMA system. A frequency agile transmitter and receiver combined with an adaptable time slot selector enables communications with remote devices utilizing different protocols. The time and frequency management capabilities of the node makes greater spectral efficiencies possible.

    ENCRYPTION APPARATUS
    114.
    发明专利
    ENCRYPTION APPARATUS 未知

    公开(公告)号：AU7859991A

    公开(公告)日：1991-10-10

    申请号：AU7859991

    申请日：1991-02-25

    Applicant: MOTOROLA INC

    Inventor： FREEBURG THOMAS A ,  WHITE RICHARD E

    IPC: H04L9/24 ,  H04L9/18 ,  H04L9/00

    Abstract: An encryption circuit that operates with substantially zero delay. Using programmable keys and polynomials, the encryption algorithm can be constantly changed to thwart any unintended receiving parties from decoding the data. A key (101) and a polynomial (102) are loaded into registers. The key is then loaded into a shift register and shifted through XOR gates (106) at a programmable rate. The other input of the XOR gates come from the result of ANDing (103) a disable signal, the polynomial register (102), and the last stage of the shift register (104). Eight bits of the shift register outputs are XOR'ed with the input data to be encrypted. The output of these XOR gates (105) is the encrypted data.

    116.
    发明专利
    未知

    公开(公告)号：BR9002502A

    公开(公告)日：1991-08-13

    申请号：BR9002502

    申请日：1990-05-28

    Applicant: MOTOROLA INC

    Inventor： FREEBURG THOMAS A

    IPC: H04L1/00 ,  H04L1/02 ,  H04L1/20

    Abstract: There is provided a scheme for bit error rate detection. It is characterised by: detecting the bit value present in a received multi-level signal (102), more narrowly detecting the bit value present in that received multi-level signal (104), comparing the results of narrow detection with the results detected otherwise to identify errors in detection (203, 206, 207 and 209), and accumulating detected symbol errors over unit time. Bit error rate detection can be used for antenna selection-selecting one of a plurality of diversity antennas when the error rate exceeds (213) a certain error threshold.

    WIRELESS IN-BUILDING TELECOMMUNICATIONS SYSTEM FOR VOICE AND DATA COMMUNICATIONS
    117.
    发明专利
    WIRELESS IN-BUILDING TELECOMMUNICATIONS SYSTEM FOR VOICE AND DATA COMMUNICATIONS 未知

    公开(公告)号：AU6904291A

    公开(公告)日：1991-06-26

    申请号：AU6904291

    申请日：1990-11-27

    Applicant: MOTOROLA INC

    Inventor： BERKEN JAMES J ,  FREEBURG THOMAS A ,  OGASAWARA ROY T ,  WHITE RICHARD E ,  MITZLAFF JAMES E ,  BEDLEK GREGORY J

    IPC: H04B7/24 ,  H04J3/00 ,  H04J3/16 ,  H04L12/28 ,  H04L12/56 ,  H04J3/24 ,  H04B1/00

    Abstract: A wireless in-building telecommunications system for voice and data communications is disclosed having at least one node (101) arranged for linking to the PSTN (151) and at least one digital information source (153, 155, 157, 159) multiplicity of user modules (103) (UM's) linked to the node via a shared RF communications path (107). Each UM is coupled to a voice telephone instrument (127) and to one or more data terminals (165). The UM's communicate with the node by exchanging fast packets via the common RF path (107). The node also includes a fast-packet-switched mechanism controlled by a bandwidth allocating scheme to prevent collisions of packets as they are transmitted between the various units (101, 103) (nodes and/or user modules) that may be accessing the RF path (107). Also disclosed is a method for allocating the required bandwidth to each of the users of the common communications path in a wireless in-building telephone system. The invention provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. It also synchronizes the transfer of the data and the allocation of bus bandwidth.

    PACKET HANDLING METHOD
    118.
    发明专利
    PACKET HANDLING METHOD 未知

    公开(公告)号：AU6890491A

    公开(公告)日：1991-06-26

    申请号：AU6890491

    申请日：1990-12-03

    Applicant: MOTOROLA INC

    Inventor： FREEBURG THOMAS A ,  KACZMARCZYK JOHN M ,  BUCHHOLZ DALE R ,  WHITE RICHARD E ,  CHANG HUNGKUN J ,  NOLAN MICHAEL P

    IPC: H04L12/54 ,  H04J3/24 ,  H04Q11/04 ,  H04Q7/00

    Abstract: In this invention a hierarchical addressing technique is employed in a packet communications system to enhance flexibility in handling packet information. This method permits packet message data (Fig. 3) and certain packet control data (Fig. 3) to be stored in memory locations (32, 34) without having to be duplicated at a different memory location prior to transmission of the packet. This method is preferably employed in a ring configuration in which a series of packets have addressing mechanisms which points sequentially to each other to form a ring of packets.

Patent Agency Ranking