ANN TRAINING TROUGH PROCESSING POWER OF PARKED VEHICLES

    公开(公告)号:US20230206071A1

    公开(公告)日:2023-06-29

    申请号:US18177689

    申请日:2023-03-02

    CPC classification number: G06N3/08 G06N3/045

    Abstract: A system for ANN training through processing power of parked vehicles. The system can include a master computing device having a controller configured to control training of an ANN. The training can be performed at least partially in separate parts by computing devices of parked vehicles. The controller can be configured to separate computing tasks of training the ANN into separated tasks. Also, the controller can be configured to assign at least some of the separated tasks to selected computing devices of parked vehicles. The controller can also be configured to receive and assemble results of the separated tasks to train the ANN. The controller can also be configured to train the ANN according to the results. The master computing device can be configured to send the assigned tasks to the selected devices of the vehicles as well as receive, from the selected devices, the results of the assigned tasks.

    Black box data recorder for autonomous driving vehicle

    公开(公告)号:US11676431B2

    公开(公告)日:2023-06-13

    申请号:US17100623

    申请日:2020-11-20

    Inventor: Gil Golov

    CPC classification number: G07C5/085 H03M7/30 H03M7/70

    Abstract: An improved black box data recorder for use with autonomous driving vehicles (AVD). In one embodiment, two cyclic buffers are provided to record vehicle sensors data. A first cyclic buffer records raw vehicle sensor data on a volatile memory, while a second cyclic buffer records the same vehicle sensor data, as compressed data, on a non-volatile memory. In a case of a collision or near collision, in one embodiment the buffers are flushed into a non-volatile (NV) storage for retrieval. As long as there is no power interruption, the raw vehicle sensor data will be accessible from the NV storage. If a power interruption occurs, the raw vehicle sensor data held in the volatile memory of the first cyclic buffer will be lost and only the compressed form of the vehicle sensor data from the second cyclic buffer will survive and be accessible.

    Data Link Between Volatile Memory and Non-Volatile Memory

    公开(公告)号:US20230076311A1

    公开(公告)日:2023-03-09

    申请号:US18054883

    申请日:2022-11-11

    Inventor: Gil Golov

    Abstract: A computing system has a first processing device (e.g., CPU, FPGA, or GPU) and memory regions (e.g., in a DRAM device) used by the processing device during normal operation. In one approach, the computing system is configured to: collect data associated with operation of an autonomous vehicle; monitor, by a first processing device, the collected data; and based on the monitoring, determine that an event on the autonomous vehicle has occurred. The computing system is further configured to, in response to determining that the event has occurred, initiate a transfer of data controlled by a second processing device, the transfer including copying data stored in volatile memory of the autonomous vehicle to non-volatile memory of the autonomous vehicle, wherein the second processing device controls copying of the data independently of the first processing device. The computing system is also further configured to, in response to determining that the event has occurred, reduce or terminate power to the first processing device.

    AUTOMATIC OPERATING MODE MANAGEMENT FOR MEMORY USING WORKLOAD PROFILE DATA

    公开(公告)号:US20220365710A1

    公开(公告)日:2022-11-17

    申请号:US17320111

    申请日:2021-05-13

    Inventor: Gil Golov

    Abstract: The disclosed embodiments relate to logging activities of memory devices and adjusting the operation of a controller based on the activities. In one embodiment, a method comprises monitoring, by a memory device, die temperatures and data sizes of commands issued to the memory device; determining, by the memory device, a target size for a buffer based on the die temperatures and data sizes; and adjusting, by the memory device, a current size of the buffer to meet the target size.

    Managed NAND flash memory region control against endurance hacking

    公开(公告)号:US11429543B2

    公开(公告)日:2022-08-30

    申请号:US17077503

    申请日:2020-10-22

    Inventor: Gil Golov

    Abstract: The disclosed embodiments are directed to improving the lifespan of a memory device. In one embodiment, a system is disclosed comprising: a host processor and a memory device, wherein the host processor is configured to receive a write command from a virtual machine, identify a region identifier associated with the virtual machine, augment the write command with the region identifier, and issue the write command to the memory device, and the memory device is configured to receive the write command, identify a region comprising a subset of addresses writable by the memory device using a region configuration table, and write the data to an address in the subset of addresses.

    STORING AND RECOVERING CRITICAL DATA IN A MEMORY DEVICE

    公开(公告)号:US20220269438A1

    公开(公告)日:2022-08-25

    申请号:US17181154

    申请日:2021-02-22

    Inventor: Gil Golov

    Abstract: The disclosed embodiments are related to storing critical data in a memory device such as Flash memory device. In one embodiment, a method performed by a controller of a memory device comprises receiving a critical operation from a host processor, the critical operation accessing a memory array; retrieving a temperature value of the memory array from a temperature sensor; and conditionally processing the critical operation based on the temperature value.

    Memory sub-system logical block address remapping

    公开(公告)号:US11416388B2

    公开(公告)日:2022-08-16

    申请号:US17027895

    申请日:2020-09-22

    Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device can determine a data rate from a first sensor and a data rate from a second sensor. The processing device can write a first set of data received from the first sensor at a first logical block address (LBA) in the memory device. The processing device can write a second set of data received from the second sensor and subsequent to the first set of data at a second LBA in the memory device. The processing device can remap the first LBA and the second LBA to be logically sequential LBAs. The second LBA can be associated with an offset from the first LBA and the offset can correspond to a data rate of the first sensor.

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