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    Validation of DRAM content using internal data signature
    1.
    发明授权
    Validation of DRAM content using internal data signature 有权

    公开(公告)号：US12080373B2

    公开(公告)日：2024-09-03

    申请号：US17562620

    申请日：2021-12-27

    Applicant: Micron Technology, Inc.

    Inventor： Gil Golov

    IPC: G11C7/06 ,  G06F21/60 ,  G06F21/78 ,  G11C7/10

    CPC classification number: G11C7/065 ,  G06F21/602 ,  G06F21/78 ,  G11C7/1039 ,  G11C7/1063

    Abstract: Systems, methods, and apparatus related to validating data stored in a memory system. In one approach, a DRAM stores data for a host device. A controller that manages the DRAM receives a command from the host device to generate a signature. The controller also receives data from the host device that indicates a region of the DRAM. In response to receiving the command, the controller reads data from the indicated region. A signature is generated by the controller based on the data read from the indicated region. The generated signature is sent to the host device in response to the command.

    PARALLEL ACCESS TO VOLATILE MEMORY BY A PROCESSING DEVICE FOR MACHINE LEARNING
    9.
    发明公开
    PARALLEL ACCESS TO VOLATILE MEMORY BY A PROCESSING DEVICE FOR MACHINE LEARNING 审中-公开

    公开(公告)号：US20230186957A1

    公开(公告)日：2023-06-15

    申请号：US18164051

    申请日：2023-02-03

    Applicant: Micron Technology, Inc.

    Inventor： Gil Golov

    IPC: G11C7/10 ,  G06N3/08 ,  G06N20/00 ,  G06N3/02 ,  G06N3/04 ,  G11C7/22

    CPC classification number: G11C7/10 ,  G06N3/08 ,  G06N20/00 ,  G06N3/02 ,  G06N3/04 ,  G11C7/22

    Abstract: A memory system having a processing device (e.g., CPU) and memory regions (e.g., in a DRAM device) on the same chip or die. The memory regions store data used by the processing device during machine learning processing (e.g., using a neural network). One or more controllers are coupled to the memory regions and configured to: read data from a first memory region (e.g., a first bank), including reading first data from the first memory region, where the first data is for use by the processing device in processing associated with machine learning; and write data to a second memory region (e.g., a second bank), including writing second data to the second memory region. The reading of the first data and writing of the second data are performed in parallel.

    Ann training through processing power of parked vehicles
    10.
    发明授权
    Ann training through processing power of parked vehicles 有权

    公开(公告)号：US11604989B2

    公开(公告)日：2023-03-14

    申请号：US16850946

    申请日：2020-04-16

    Applicant: Micron Technology, Inc.

    Inventor： Gil Golov ,  Robert Richard Noel Bielby

    IPC: G08G1/01 ,  G06N3/08 ,  G06N3/04

    Abstract: A system for ANN training through processing power of parked vehicles. The system can include a master computing device having a controller configured to control training of an ANN. The training can be performed at least partially in separate parts by computing devices of parked vehicles. The controller can be configured to separate computing tasks of training the ANN into separated tasks. Also, the controller can be configured to assign at least some of the separated tasks to selected computing devices of parked vehicles. The controller can also be configured to receive and assemble results of the separated tasks to train the ANN. The controller can also be configured to train the ANN according to the results. The master computing device can be configured to send the assigned tasks to the selected devices of the vehicles as well as receive, from the selected devices, the results of the assigned tasks.

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