公开(公告)号：JPH1145336A

公开(公告)日：1999-02-16

申请号：JP21544797

申请日：1997-07-28

Applicant: NEC CORP

Inventor： UCHIDA KAORU

IPC: G06T7/00 ,  G06K9/00 ,  G06T3/00

Abstract: PROBLEM TO BE SOLVED: To support exact inputs when an operator manually inputs or corrects fine structure such as ridge line shape, end point or branch point to a low- quality image. SOLUTION: A source image is held in an image holding part 11 and presented to the operator by an image presenting part 12. Concerning the concerned part of the source image, the operator inputs a rotating direction and a compression ratio for watching a ridge line group better from a viewpoint converting instruction input part 13. According to this information, a viewpoint conversion calculating part 14 generates the result image through glance conversion (affin transformation) and presents it through a viewpoint converted image presenting part 15 to a user. While referring to that image, the operator executes work such as manual plot or manual trace and the result is inputted from a manual input part 16, recorded, converted into feature data by a feature data converting part 17 and outputted.

公开(公告)号：JPH0311479A

公开(公告)日：1991-01-18

申请号：JP14515689

申请日：1989-06-09

Applicant: NEC CORP

Inventor： UCHIDA KAORU

IPC: G06F15/82

Abstract: PURPOSE:To perform cumulative addition in a data processor which links a memory part to an arithmetic part and controls arithmetic sequence with a data driving system by using the addition instruction of a stream, attaching a termination mark on the last position of the stream, and performing the arithmetic operation of the stream when performing the arithmetic control of a token. CONSTITUTION:A data processor is operated according to the token inputted via a bus token input part 11, and a result is stored in a link table 12. A data part 64 having a data value to be processed, a link table address 63 for token identification, and the termination mark 62 to represent the termination of the stream are provided at the table 12, and plural tokens having the same link table address are outputted as keeping sequence with each other. Also, the token is fetched in a table address to be provided after the arithmetic operation, an address to refer to a stream arithmetic operation completion detector 1, and the table 12 before receiving the arithmetic operation at a processing unit 16.

公开(公告)号：JPH02282876A

公开(公告)日：1990-11-20

申请号：JP10340289

申请日：1989-04-25

Applicant: NEC CORP

Inventor： UCHIDA KAORU

IPC: G06F15/82

Abstract: PURPOSE:To obtain a subroutine mechanism that can be called from plural places by producing a token containing the result data and a link table address to serve as a return destination out of paired tokens. CONSTITUTION:A token identifier converter 21 consists of an input token register 22, a conversion controller 24, an address register 25, and a multiplexer 26. When an identifier for paired tokens is converted on an internal bus, the value of link table addresses of the tokens are selectively converted. In this process applying a subroutine transformation method, the paired tokens containing the result data and the link table addresses to serve as the return addresses are produced from other paired tokens as the converted tokens. These produced tokens are sent to the return arc of a main program. Thus it is possible to obtain a subroutine mechanism that can be called from plural places.

公开(公告)号：JPS649559A

公开(公告)日：1989-01-12

申请号：JP16401187

申请日：1987-07-02

Applicant: NEC CORP

Inventor： UCHIDA KAORU

IPC: G06F13/42 ,  G06F9/44 ,  G06F15/82

Abstract: PURPOSE:To attain write without being interfered with other write token by outputting a write data and an address as a set token to an external bus consecutively and giving it while keeping the consecution in passing through other processor. CONSTITUTION:In applying write to a memory, a token having a write data and a token having a write address are awaited in a data flow processor 1 to generate a set token. The set token is outputted to an external bus in a token output section 17 while the token passing through the processor is not interrupted inbetween. A set token whose destination from a data flow processor of the pre-stage is other than the said processor is given to the token output section of the data processor and in outputting it to the external bus, the output token from its own processor is controlled so as not to be interfered with the set tokens. Thus, the intentional write is guaranteed.

公开(公告)号：JPS63173141A

公开(公告)日：1988-07-16

申请号：JP399287

申请日：1987-01-13

Applicant: NEC CORP

Inventor： UCHIDA KAORU

IPC: G06F12/00 ,  G06F9/44 ,  G06F15/82

Abstract: PURPOSE:To realize an exact write operation, by inputting an incremental write (IW) address set token and an IW token from a data flow processor to an interface circuit. CONSTITUTION:When an incremental operation is performed, a data flag and an IW flag input the IW address write set tokens of 0 and 1 from the data porcessor 22 a memory interface circuit 10 respectively. In a circuit 10, an address which becomes the base of the IW is set at an address register 11 by setting a latch signal S118 to the address register 11 at 1. Next, the number of times of write of the IW token is inputted from the processor 22 to the circuit 10. The circuit 10, after completing the input/output operation of the token, latches the data on a register 13 by setting a latch signal S117 to a register 13 at 1, and writes the value of the register 11 on a memory 20 by setting a memory read/write signal S105 at 1.

公开(公告)号：JPS6395540A

公开(公告)日：1988-04-26

申请号：JP24163086

申请日：1986-10-09

Applicant: NEC CORP

Inventor： UCHIDA KAORU

IPC: G06F15/82 ,  G06F9/44 ,  G06F12/00

Abstract: PURPOSE:To shorten the processing time by using a memory interface circuit containing plural data processors, a memory and a token input part to perform the memory reading/writing actions. CONSTITUTION:In a memory interface circuit 10, the value of an address register 11 is used as an address to read a memory 20 based on the decoding result of the tokens supplied to a token input part 16 from data processors 21 and 22 in case an identifier showing a read token containing a read address is prepared together with a flag showing execution of the indirect addressing and a data part serving as the read address. While the set value of the register 11 is used as an address and the value of a data register 13 is written into the memory 20 in case an identifier showing a write token containing a write address is prepared together with a flag showing execution of the indirect addressing and a data part serving as the write address. In such a way, the processing speed is increased with a memory interface circuit.