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公开(公告)号：JP2009124762A
公开(公告)日：2009-06-04
申请号：JP2009057331
申请日：2009-03-11
Inventor： OKADA TAKAHIRO , IKEDA YASUNARI
Abstract: PROBLEM TO BE SOLVED: To prevent the effect suffered from adjacent channels even in the case of no guard band, in a transmitter.
SOLUTION: In the transmitter, an information sequence 1 inputted to a mapping device 21-1 is so mapped into a predetermined signal point as to be outputted to a frequency converter 22-1. The frequency converter 22-1 so frequency-converts the inputted signal in response to its intermediate frequency as to output it to a multiplexer 23. Information sequences 2, 3 are so treated respectively similarly to the information sequence 1 as to be outputted to the multiplexer 23. The multiplexer 23 so multiplexes the inputted signals that an IFFT operator 24 inverse-Fourier-transforms the multiplexed signals in a lump. The inverse-Fourier-transformed signal is so orthogonal-modulated by an orthogonal modulator 26 and is so transformed further into an RF-band signal by a frequency modulator 28 as to be transformed via an antenna 30.
COPYRIGHT: (C)2009,JPO&INPITAbstract translation: 要解决的问题：即使在无保护频带的情况下，也可以在发射机中防止相邻信道所遭受的影响。 解决方案：在发射机中，输入到映射设备21-1的信息序列1被映射到预定的信号点，以被输出到频率转换器22-1。 频率转换器22-1根据其中频对输入的信号进行频率转换，以将其输出到多路复用器23.信息序列2,3分别类似于信息序列1被处理以被输出到多路复用器 复用器23多路复用输入信号，即IFFT运算符24对多路复用信号进行一次一体的傅里叶变换。 逆傅里叶变换信号由正交调制器26进行正交调制，并且由频率调制器28进一步变换成RF频带信号，以经由天线30变换。（C） 2009年，JPO＆INPIT
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公开(公告)号：JP2007318781A
公开(公告)日：2007-12-06
申请号：JP2007172482
申请日：2007-06-29
Inventor： IKEDA YASUNARI , IKEDA TAMOTSU
Abstract: PROBLEM TO BE SOLVED: To perform stable reproduction by improving immunity to transmission line error regarding a control signal related to transmission such as a TMCC (Transmission Multiplexing Configuration Control) signal, for example. SOLUTION: In a digital broadcast signal receiving apparatus which receives a digital broadcasting signal in which a control signal (TMCC signal) related to a transmission system is transmitted together with a main signal, a received signal is demodulated by a demapping circuit 43, and the TMCC signal and the main signal are decoded by a viterbi decoding circuit 44. A TMCC decoder 47 decodes the TMCC signal from a signal outputted from the viterbi decoding circuit 44 and inputted through a deinterleave circuit 45 and a Reed-Solomon decoding circuit 46, extracts transmission control information such as a modulation scheme or a coding rate of the main signal and outputs it to the demapping circuit 43 and the viterbi decoding circuit 44. COPYRIGHT: (C)2008,JPO&INPIT
Abstract translation: 要解决的问题：例如，通过提高与诸如TMCC（传输多路复用配置控制）信号的传输相关的控制信号的传输线路误差的抗扰性来执行稳定再现。 解决方案：在接收与主信号一起发送与发送系统相关的控制信号（TMCC信号）的数字广播信号的数字广播信号接收装置中，接收信号由解映射电路43解调 ，TMCC信号和主信号由维特比解码电路44解码.TMCC解码器47根据从维特比解码电路44输出的信号对TMCC信号进行解码，并通过解交织电路45和里德 - 所罗门解码电路 提取诸如主信号的调制方式或编码率的传输控制信息，并将其输出到解映射电路43和维特比解码电路44.（C）2008年，JPO和INPIT
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公开(公告)号：JP2004343586A
公开(公告)日：2004-12-02
申请号：JP2003139874
申请日：2003-05-19
Inventor： IKEDA YASUNARI
Abstract: PROBLEM TO BE SOLVED: To provide a receiving apparatus and method whereby the number of branches for applying diversity reception to an OFDM (Orthogonal Frequency Division Multiplexing) signal can easily be revised.
SOLUTION: Received power detection circuits 24-1, 24-2 respectively detect power levels of transmission signals A, B by each OFDM symbol and inform a weight control circuit 12 about the detected power levels. The weight control circuit 12 calculates respective weight coefficients of branches 11-1, 11-2 on the basis of the power levels of the transmission signals A, B by each OFDM symbol. Weighting circuits 29-1, 29-2 multiply the weight coefficients with frequency region signals outputted from FFT (Fast Fourier Transform) circuits 27-1, 27-2 to weight the frequency region signals. Equalization circuits 31-1, 31-2 equalize the weighted frequency region signals and thereafter an adder circuit 13 additively composes the equalized and weighted frequency region signals. The receiving apparatus and method are applicable to electronic apparatuses for receiving OFDM signals.
COPYRIGHT: (C)2005,JPO&NCIPI-
公开(公告)号：JP2004343585A
公开(公告)日：2004-12-02
申请号：JP2003139873
申请日：2003-05-19
Inventor： IKEDA YASUNARI
Abstract: PROBLEM TO BE SOLVED: To provide a receiving apparatus capable of improving the C/N ratio of a received OFDM signal and the error correction capability. SOLUTION: An equalization control circuit 12 calculates transfer functions of equalization circuits 27-1, 27-2 on the basis of a characteristic of a transmission path supplied from transmission path characteristic estimate circuits 26-1, 26-2 and respectively supplies the transfer functions to the equalization circuits 27-1, 27-2, calculates a metric control value to apply weighting to a path metric on the basis of the characteristic of the transmission path and supplies the metric control value to a Viterbi decoding circuit 41. An adder circuit 13 additively composes outputs from the equalization circuits 27-1, 27-2 so that the outputs of the equalization circuits 27-1, 27-2 are composed at a maximum ratio, and the composed signal is fed to the Viterbi decoding circuit 41. The Viterbi decoding circuit 41 calculates the path metric and multiplies the metric control value with the path metric to apply weighting to the path metric by each OFDM carrier. The receiving apparatus and method are applicable to electronic apparatuses for receiving OFDM signals. COPYRIGHT: (C)2005,JPO&NCIPI
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公开(公告)号：JP2004214962A
公开(公告)日：2004-07-29
申请号：JP2002382213
申请日：2002-12-27
Inventor： YAJIMA ATSUSHI , FUNAMOTO KAZUHISA , IKEDA YASUNARI
CPC classification number: H04L27/2605 , H04L7/02 , H04L27/2662 , H04L27/2676
Abstract: PROBLEM TO BE SOLVED: To provide an OFDM (Orthogonal Frequency Division Multiplexing) demodulator capable of detecting correctly clock frequency errors. SOLUTION: The OFDM receiving system 1 is equipped with a clock frequency error calculating circuit 41 for calculating clock frequency errors between a received signal clock and an operating clock inside the system, and a guard correlation/peak detecting circuit 12 for determining autocorrelation of guard intervals to detect a peak timing of the correlation signal. The guard correlation/ peak detecting circuit 12 includes an automatic counter in its inside to output an automatic counter value at the peak timing to the clock frequency error calculating circuit 41, which calculates a time change rate of the input counter value using a plurality of time change rate detecting circuits that are set at different measurement intervals. The clock frequency error calculating circuit 41 makes the time change rate into a histogram, from which the clock frequency errors are calculated. COPYRIGHT: (C)2004,JPO&NCIPI
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Patent Agency Ranking
公开(公告)号：JP2004214961A
公开(公告)日：2004-07-29
申请号：JP2002382212
申请日：2002-12-27
Inventor： FUNAMOTO KAZUHISA , OKADA TAKAHIRO , IKEDA TAMOTSU , YAJIMA ATSUSHI , IKEDA YASUNARI
CPC classification number: H04L27/2605 , H04L27/2657 , H04L27/2662 , H04L27/2676
Abstract: PROBLEM TO BE SOLVED: To perform a symbol synchronizing processing utilizing only the correlation value of a guard interval and to improve the synchronizing accuracy. SOLUTION: An OFDM (orthogonal frequency multi-division modulation) demodulator 1 is provided with a guard correlation/peak detection circuit 12 for generating the peak timing Np of the correlation value of the guard interval and a timing synchronizing circuit 13 for estimating a symbol boundary timing Nx from the peak timing Np. The timing synchronizing circuit 13 performs filtering by a DLL (delay locked loop) 43 to Np and calculates the symbol boundary timing Nx. Further, the DLL 43 is provided with a limiter 52 for limiting the range of a phase error component and an asymmetrical gain circuit 53 for changing the size of a gain corresponding to the polarity of a phase error, thereby preventing a timing step-out due to phasing and multipath. COPYRIGHT: (C)2004,JPO&NCIPI
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公开(公告)号：JP2002111762A
公开(公告)日：2002-04-12
申请号：JP2000292844
申请日：2000-09-26
Applicant: SONY CORP
Inventor： IKEDA TAMOTSU , OZAKI YASUNARI , IKEDA YASUNARI
Abstract: PROBLEM TO BE SOLVED: To securely pull in synchronism of the synchronous timing of a transmission symbol at high speed. SOLUTION: In the demodulating device of a digital quadrature modulated signal, a clock which is synchronized with a timing synchronizing signal and whose frequency is higher than that of the timing synchronizing signal is used as a sampling clock at the time of sampling a PSK modulated signal. Timing in the middle of synchronous timing and synchronous timing, namely, timing whose phase is shifted 180 deg. from synchronous timing is set to be the center and signal points shifted from the center by the same phase amounts in a plus direction and a minus direction are detected from the PSK modulated signal obtained by sampling. Power values are obtained from the detected signal points and the level difference of the power values of the two signal points is detected. The detected level difference is hourly averaged. The level difference which is thus obtained is used as a phase difference.
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公开(公告)号：JP2001313627A
公开(公告)日：2001-11-09
申请号：JP2000134312
申请日：2000-04-28
Applicant: SONY CORP
Inventor： OKADA TAKAHIRO , MOMOSHIRO TOSHIHISA , MIYATO YOSHIKAZU , IKEDA YASUNARI
Abstract: PROBLEM TO BE SOLVED: To perform waveform equalization with high accuracy when connecting and transmitting ISDB-Ts. SOLUTION: Information for discriminating whether an adjacent segment is a synchronous segment or a differential segment is described in TMCC information at the time of performing connection transmission. A receiver refers to the TMCC information, and when the adjacent segment is the synchronous segment, the receiver estimates the transmission characteristic of a transmission path and performs waveform equalization by using an SP signal including an adjacent channel, too. Specifically, a timing control circuit 59 decides whether the SP signal is included in the adjacent channel, and when the SP signal is included, a frequency direction filter 56 performs FIR filtering and corrects a signal of a frequency direction by using not only the SP signal inserted into a frequency channel to be a demodulation channel but also the SP signal of the adjacent channel.
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公开(公告)号：JPH11252190A
公开(公告)日：1999-09-17
申请号：JP4920398
申请日：1998-03-02
Applicant: SONY CORP
Inventor： IKEDA YASUNARI
Abstract: PROBLEM TO BE SOLVED: To detect a unique word with high accuracy. SOLUTION: An (i) signal processed by a carrier for an in-phase signal in an orthogonal demodulation circuit becomes a variable of a real part. When the (i) signal is given to a unique word detection circuit 20, the signal is delayed by one symbol by n-sets of registers 31-1-31-n and extracted and prescribed tap coefficients u1-un are multiplied with the signal by multipliers 32-1-32-n. The results of multiplication are added by adders 33-1-33-n respectively. A (q) signal processed by the orthogonal signal carrier becomes a variable of an imaginary part. When the (q) signal is given to the unique word detection circuit 20, the signal is delayed by one symbol by n-sets of registers 35-1-35-n and extracted and prescribed tap coefficients u1-un are multiplied with the signal by multipliers 36-1-36-n. The results of multiplication are added by adders 37-1-37-n, respectively.
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公开(公告)号：JPH10307811A
公开(公告)日：1998-11-17
申请号：JP11471397
申请日：1997-05-02
Applicant: SONY CORP
Inventor： OZAKI YASUNARI , IKEDA YASUNARI
IPC: G06F17/14
Abstract: PROBLEM TO BE SOLVED: To execute the butterfly operation of radixes '4' and '2' by the same circuit. SOLUTION: In the case of executing the butterfly operation of a radix '2', signal lines shown by broken lines are removed by a selector or the like and respective multipliers of a signal line connecting a complex multiplying circuit 1 to a complex adding circuit 5, a signal line connecting a complex multiplying circuit 2 to a complex adding circuit 7, a signal line connecting a complex multiplying circuit 3 to a complex adding circuit 6, and a signal line connecting the circuit 3 to the circuit 7 are respectively changed from -j, -1, -1, -j to -1, 1, 1, -1. As the result of changes, two batterfly operation circuit groups A, B are formed. In the case of executing the operation of a radix '4', all signal lines shown by broken lines are connected and the multipliers of respective passes are set up as shown in the figure. As the result, one radix-four batterfly operation circuit is formed.
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