公开(公告)号：US10685912B2

公开(公告)日：2020-06-16

申请号：US16270356

申请日：2019-02-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/522

Abstract: An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization levels separated by an insulating region; and an antifuse structure coated with a portion of the insulating region, the antifuse structure comprising a beam held at two different points by two arms, a body, and an antifuse insulating zone, the beam, the body and the arms being metal and located within a same metallization level, the body and the beam mutually making contact via the antifuse insulating zone, the antifuse insulating zone configured to undergo breakdown in the presence of a breakdown potential difference between the body and the beam.

公开(公告)号：US20200083011A1

公开(公告)日：2020-03-12

申请号：US16680940

申请日：2019-11-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio Di-Giacomo ,  Brice Arrazat

IPC: H01H59/00 ,  H01H57/00 ,  B81C1/00 ,  H01L27/06 ,  H01H1/00 ,  H01L21/822

Abstract: Methods of operating a switching device are provided. The switching device is formed in an interconnect, the interconnect including a plurality of metallization levels, and has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure.

公开(公告)号：US10580498B2

公开(公告)日：2020-03-03

申请号：US15886243

申请日：2018-02-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/00 ,  G11C16/22 ,  H01L21/74 ,  H01L21/8238 ,  G06F21/87 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/66 ,  H01L27/115 ,  H01L29/78

Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.

公开(公告)号：US10475713B2

公开(公告)日：2019-11-12

申请号：US15648135

申请日：2017-07-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/04 ,  H01L23/522 ,  H01L49/02 ,  B81B3/00 ,  H01G5/18 ,  H01L27/06

Abstract: An integrated circuit includes several metallization levels separated by an insulating region. A hollow housing whose walls comprise metallic portions is produced within various metallization levels. A controllable capacitive device includes a suspended metallic structure situated in the hollow housing within a first metallization level including a first element fixed on two fixing zones of the housing and at least one second element extending in cantilever fashion from the first element and includes a first electrode of the capacitive device. A second electrode includes a first fixed body situated at a second metallization level adjacent to the first metallization level facing the first electrode. The first element is controllable in flexion from a control zone of this first element so as to modify the distance between the two electrodes.

公开(公告)号：US10283648B2

公开(公告)日：2019-05-07

申请号：US15704617

申请日：2017-09-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara

IPC: G11C17/16 ,  H01L27/12 ,  H01L23/525 ,  H01L27/112 ,  H01L29/8605 ,  H01L27/06 ,  H01L29/06

Abstract: A fuse device is formed by a PN junction semiconducting region that is electrically insulated from other portions of an integrated circuit. The fuse device includes a first semiconducting zone having P type of conductivity and a second semiconducting zone having N type of conductivity in contact at a PN junction. First and second electrically conducting contact zones are provided on the first and second semiconducting zone, respectively, without making contact with the PN junction. One of the first and second semiconducting zones is configured with a non-homogeneous concentration of dopants, where a region with a lower value of concentration of dopant is located at the PN junction and a region with a higher value of concentration of dopant is locates at the corresponding electrically conducting contact zone.

公开(公告)号：US20180254353A1

公开(公告)日：2018-09-06

申请号：US15704617

申请日：2017-09-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara

IPC: H01L29/8605 ,  H01L29/06 ,  H01L27/06 ,  H01L27/12

CPC classification number: H01L29/8605 ,  G11C17/16 ,  G11C17/18 ,  G11C2207/2254 ,  H01L23/5256 ,  H01L27/0629 ,  H01L27/11206 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/861

Abstract: A fuse device is formed by a PN junction semiconducting region that is electrically insulated from other portions of an integrated circuit. The fuse device includes a first semiconducting zone having P type of conductivity and a second semiconducting zone having N type of conductivity in contact at a PN junction. First and second electrically conducting contact zones are provided on the first and second semiconducting zone, respectively, without making contact with the PN junction. One of the first and second semiconducting zones is configured with a non-homogeneous concentration of dopants, where a region with a lower value of concentration of dopant is located at the PN junction and a region with a higher value of concentration of dopant is locates at the corresponding electrically conducting contact zone.

公开(公告)号：US20180145027A1

公开(公告)日：2018-05-24

申请号：US15596877

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/7685 ,  H01L21/76883 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/573

Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer and an inter-metallization level insulating layer. An electrical discontinuity is provided between a via of the via level and a metal track of the lower metallization level. The electrical discontinuity is formed by an additional insulating layer having a material composition identical to that of the inter-metallization level insulating layer. The electrical discontinuity is situated between a bottom of the via and a top of the metal track, with the discontinuity being bordered by the insulating encapsulation layer.

公开(公告)号：US20180136611A1

公开(公告)日：2018-05-17

申请号：US15868484

申请日：2018-01-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara

IPC: G04F10/10 ,  H01L27/115 ,  H01L29/788 ,  H01L21/28 ,  H01L29/51 ,  G11C16/34 ,  G11C16/28 ,  G11C16/04 ,  H01L27/11521 ,  G11C27/00 ,  H01L29/66 ,  H01L27/11524

CPC classification number: G04F10/10 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/28 ,  G11C16/349 ,  G11C27/005 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/788

Abstract: An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.

公开(公告)号：US20180130740A1

公开(公告)日：2018-05-10

申请号：US15610323

申请日：2017-05-31

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/525 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5252 ,  H01L21/76877 ,  H01L23/5226

Abstract: An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization levels separated by an insulating region; and an antifuse structure coated with a portion of the insulating region, the antifuse structure comprising a beam held at two different points by two arms, a body, and an antifuse insulating zone, the beam, the body and the arms being metal and located within a same metallization level, the body and the beam mutually making contact via the antifuse insulating zone, the antifuse insulating zone configured to undergo breakdown in the presence of a breakdown potential difference between the body and the beam.

公开(公告)号：US09954119B2

公开(公告)日：2018-04-24

申请号：US15402758

申请日：2017-01-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Roberto Simola ,  Pascal Fornara

IPC: H01L29/866 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/66

CPC classification number: H01L29/866 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66106 ,  H01L29/7391

Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.