公开(公告)号：US10312242B2

公开(公告)日：2019-06-04

申请号：US15986780

申请日：2018-05-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chieh Chen ,  Pin-Hong Chen ,  Chih-Chieh Tsai ,  Chia-Chen Wu ,  Yi-An Huang ,  Kai-Jiun Chang ,  Tsun-Min Cheng ,  Yi-Wei Chen

IPC: H01L23/31 ,  H01L27/108

Abstract: A semiconductor memory device is provided, and which includes a substrate, plural gates, plural plugs, a capacitor structure and a conducting cap layer. The gates are disposed within the substrate, and the plugs are disposed on the substrate, with each plug electrically connected to two sides of each gate on the substrate. The capacitor structure is disposed on the substrate, and the capacitor structure includes plural capacitors, with each capacitor electrically connected to the plugs respectively. The conducting cap layer covers the top surface and sidewalls of the capacitor structure. Also, the semiconductor memory device further includes an adhesion layer and an insulating layer. The adhesion layer covers the conducting cap layer and the capacitor structure, and the insulating layer covers the adhesion layer.

公开(公告)号：US10276389B1

公开(公告)日：2019-04-30

申请号：US15987887

申请日：2018-05-23

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chieh Tsai ,  Yi-Wei Chen ,  Pin-Hong Chen ,  Chih-Chien Liu ,  Tzu-Chieh Chen ,  Chun-Chieh Chiu ,  Tsun-Min Cheng ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L21/28 ,  H01L21/768 ,  H01L29/49 ,  H01L27/108

Abstract: A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a first metal silicon nitride layer on the silicon layer; performing an oxygen treatment process to form an oxide layer on the first metal silicon nitride layer; forming a second metal silicon nitride layer on the oxide layer; forming a conductive layer on the second metal silicon nitride layer; and patterning the conductive layer, the second metal silicon nitride layer, the oxide layer, the first metal silicon nitride layer, and the silicon layer to form a gate structure.

公开(公告)号：US10249706B1

公开(公告)日：2019-04-02

申请号：US15951185

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Lung Chang ,  Wei-Hsin Liu ,  Po-Chun Chen ,  Yi-Wei Chen ,  Han-Yung Tsai ,  Tzu-Chin Wu ,  Shih-Fang Tzou

IPC: H01L49/02 ,  H01L27/108

Abstract: The present invention provides a semiconductor structure comprising a substrate, a cell region defined on the substrate, a plurality of lower electrodes of the capacitor structures located in the cell region, an top support structure, contacting a top region of the lower electrode structure, and at least one middle support structure located between the substrate and the top support structure, contacting a middle region of the lower electrode structure, wherein when viewed in a top view, the top support structure and the middle support structure do not completely overlapped with each other.

公开(公告)号：US20180337187A1

公开(公告)日：2018-11-22

申请号：US16028364

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chieh Tsai ,  Pin-Hong Chen ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L27/108

Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.

公开(公告)号：US10043811B1

公开(公告)日：2018-08-07

申请号：US15627455

申请日：2017-06-20

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chieh Tsai ,  Pin-Hong Chen ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L27/108

Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.

公开(公告)号：US20180190658A1

公开(公告)日：2018-07-05

申请号：US15859766

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Mei-Ling Chen ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Ching-Hsiang Chang ,  Tzu-Chin Wu ,  Shih-Fang Tzou

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76834 ,  H01L21/02112 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02348 ,  H01L21/76825 ,  H01L21/823475 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/87 ,  H01L28/91

Abstract: The present invention provides a method for fabricating a semiconductor device, comprising at least the steps of: providing a substrate in which a memory region and a peripheral region are defined, the memory region includes a plurality of memory cells, each memory cell includes at least a first transistor and a capacitor, the peripheral region compress a second transistor, a first insulating layer is formed within the memory region and the peripheral region by an atomic layer deposition process, covering the capacitor of the memory cells in the memory region and the second transistor in the peripheral region, and a second insulating layer is formed, overlying the first insulating layer and the peripheral region. Finally, a contact structure is formed within the second insulating layer, and electrically connecting the second transistor.

公开(公告)号：US09929134B2

公开(公告)日：2018-03-27

申请号：US14817186

申请日：2015-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a cell region defined thereon, in which the cell region includes a first edge and a second edge extending along a first direction; and a plurality of patterns on the substrate extending along the first direction, in which the patterns includes a plurality of first patterns and a plurality of second patterns, and one of the first patterns closest to the first edge and one of the second patterns closest to the second edge are different.

公开(公告)号：US09859170B2

公开(公告)日：2018-01-02

申请号：US15434067

申请日：2017-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Wei-Cyuan Lo ,  Ming-Jui Chen ,  Chia-Lin Lu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Tan-Ya Yin ,  Chia-Wei Huang ,  Shu-Ru Wang ,  Yung-Feng Cheng

IPC: H01L21/8238 ,  H01L21/768 ,  H01L27/11 ,  H01L23/535 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823871 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

公开(公告)号：US09773789B1

公开(公告)日：2017-09-26

申请号：US15260292

申请日：2016-09-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Kai-Jiun Chang

IPC: H01L29/49 ,  H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10897

Abstract: A dynamic random access memory (DRAM) device includes a substrate, plural buried gates and plural bit lines. The buried gates are disposed in the substrate along a first trench extending along a first direction. The bit lines are disposed over the buried gates and extending along a second direction across the first direction. Each of the bit lines includes a multi-composition barrier layer, wherein the multi-composition barrier layer includes WSixNy with x and y being greater than 0 and the multi-composition barrier layer is silicon-rich at a bottom portion thereof and is nitrogen-rich at a top portion thereof.

公开(公告)号：US09722030B1

公开(公告)日：2017-08-01

申请号：US15175045

申请日：2016-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Yi-Wei Chen ,  I-Cheng Hu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/165 ,  H01L29/167 ,  H01L23/528 ,  H01L23/532 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/324 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53252 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.