公开(公告)号：US20180286867A1

公开(公告)日：2018-10-04

申请号：US15937849

申请日：2018-03-27

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Wang Zhan

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/311

Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a dielectric layer is formed on a semiconductor substrate, and a conductive pad is formed in the dielectric layer. Then, a stacked structure is formed on the dielectric layer, and the stacked structure includes a first layer, a second layer and a third layer stacked one over another on the conductive pad. Next, a patterned mask layer is formed on the stacked structure, and a portion of the stacked structure is removed, to form an opening in the stacked structure, with the opening having a taped sidewall in the second layer and the first layer. After that, the taped sidewall of the opening in the second layer is vertically etched, to form a contact opening in the stacked structure. Finally, the patterned mask layer is removed.

公开(公告)号：US10062613B1

公开(公告)日：2018-08-28

申请号：US15611759

申请日：2017-06-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Yu-Cheng Tung ,  Ming-Feng Kuo ,  Li-Chiang Chen

IPC: H01L27/108 ,  H01L29/51 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L21/823456 ,  H01L21/82345 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first trench and a second trench in a substrate; forming a first work function metal layer in the first trench and the second trench; forming a patterned mask to cover the second trench; removing the first work function metal layer from the first trench; forming a second work function metal layer in the first trench and the second trench; and forming a conductive layer in the first trench and the second trench to form a first gate structure and a second gate structure.

公开(公告)号：US20180197863A1

公开(公告)日：2018-07-12

申请号：US15859763

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/311 ,  H01L21/033 ,  H01L49/02 ,  H01L21/027 ,  H01L21/02

CPC classification number: H01L27/1085 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/87 ,  H01L28/91

Abstract: A method for fabricating a capacitor includes providing a substrate and a first etching stop layer on the substrate; forming a plurality of first spacers on the first etching stop layer; forming an organic layer and a second etching stop layer sequentially on the first spacers, the organic layer covering the first spacers; forming a plurality of second spacers on the second etching stop layer, each second spacer crossing the first spacers; transferring a pattern of the second spacers to the organic layer to form an organic pattern; performing an etching process using the organic pattern and the first spacers as a mask to form an etching stop pattern and remove the second etching stop layer; transferring the etching stop pattern to the substrate to form a plurality of through holes.

公开(公告)号：US20180190663A1

公开(公告)日：2018-07-05

申请号：US15458946

申请日：2017-03-14

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chien-Cheng Tsai ,  Feng-Ming Huang ,  Hsien-Shih Chu

IPC: H01L27/108

CPC classification number: H01L27/1085 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/10847 ,  H01L27/10882 ,  H01L27/10888

Abstract: A manufacturing method of a semiconductor storage device includes forming a plurality of bit line structures on a semiconductor substrate and forming a plurality of storage node contacts disposed between the bit line structures. The method of forming the storage node contacts includes forming a plurality of conductive patterns on the semiconductor substrate followed by performing an etching back process to the conductive patterns for decreasing a thickness of the conductive patterns. The manufacturing method further includes forming a plurality of isolation patterns between the conductive patterns, wherein the isolation patterns are formed after forming the plurality of conductive patterns and before the etching back process. According to the present invention, the storage node contacts are formed by first forming the conductive patterns and then forming the isolation patterns between the conductive patterns, so as to simplify manufacturing process and increase process yield.

公开(公告)号：US20180190657A1

公开(公告)日：2018-07-05

申请号：US15856084

申请日：2017-12-28

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Wang Zhan ,  Chieh-Te Chen

IPC: H01L27/108 ,  H01L21/311 ,  H01L21/02 ,  H01L49/02

CPC classification number: H01L27/10814 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/31116 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/91

Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.

公开(公告)号：US20180190586A1

公开(公告)日：2018-07-05

申请号：US15856089

申请日：2017-12-28

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Chien-Cheng Tsai ,  Feng-Ming Huang

IPC: H01L23/528 ,  H01L29/06 ,  H01L23/522 ,  H01L21/768 ,  H01L21/762 ,  H01L21/311

CPC classification number: H01L23/5283 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/0649

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

公开(公告)号：US20180012975A1

公开(公告)日：2018-01-11

申请号：US15677029

申请日：2017-08-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Wei-Hao Huang

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.

公开(公告)号：US20170133274A1

公开(公告)日：2017-05-11

申请号：US14963216

申请日：2015-12-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Shih-Fang Tzou ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Wei-Hao Huang

IPC: H01L21/8234 ,  H01L27/092 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/31116 ,  H01L21/76897 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure and a second gate structure on the substrate; forming a contact etch stop layer (CESL) on the first gate structure, the second gate structure, and the substrate; removing part of the CESL between the first gate structure and the second gate structure; and forming an interlayer dielectric (ILD) layer on the CESL.

公开(公告)号：US20170069528A1

公开(公告)日：2017-03-09

申请号：US14845294

申请日：2015-09-04

Applicant: United Microelectronics Corp.

Inventor： Wei-Hao Huang ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Shang-Yuan Tsai

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/41791 ,  H01L2029/7858

Abstract: The present invention provides a method for forming an opening, including: first, a hard mask material layer is formed on a target layer, next, a tri-layer hard mask is formed on the hard mask material layer, where the tri-layer hard mask includes an bottom organic layer (ODL), a middle silicon-containing hard mask bottom anti-reflection coating (SHB) layer and a top photoresist layer, and an etching process is then performed, to remove parts of the tri-layer hard mask, parts of the hard mask material layer and parts of the target layer in sequence, so as to form at least one opening in the target layer, where during the step for removing parts of the hard mask material layer, a lateral etching rate of the hard mask material layer is smaller than a lateral etching rate of the ODL.

Abstract translation: 本发明提供一种形成开口的方法，包括：首先在目标层上形成硬掩模材料层，接着在硬掩模材料层上形成三层硬掩模，其中三层硬 掩模包括底部有机层（ODL），中间含硅硬掩模底部防反射涂层（SHB）层和顶部光致抗蚀剂层，然后进行蚀刻工艺以除去三层硬掩模的部分 ，硬掩模材料层的一部分和目标层的一部分，以便在目标层中形成至少一个开口，其中在用于去除硬掩模材料层的部分的步骤期间，侧面蚀刻速率为 硬掩模材料层小于ODL的横向蚀刻速率。

公开(公告)号：US09583388B2

公开(公告)日：2017-02-28

申请号：US14591936

申请日：2015-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在栅极结构上形成牺牲层; 在牺牲层和ILD层中形成第一接触塞; 去除牺牲层; 以及在所述栅极结构和所述第一接触插塞上形成第一电介质层。