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111.发明授权公开(公告)号：US09992916B2
公开(公告)日：2018-06-05
申请号：US14595391
申请日：2015-01-13
Inventor： Giovanni Luca Torrisi , Domenico Massimo Porto , Sergio Lecce , Manuel Gaertner
CPC classification number: H05K7/20945 , H01L23/34 , H01L2924/0002 , H03K2017/0806 , Y10T307/773 , H01L2924/00
Abstract: A thermal control process for an electronic power device including a multi-junction integrated circuit may include defining a first and at least one second groups of junctions, with each group including one first and at least one second junctions, and associating a thermal detector with each group. A first group control may be executed which detects group electric signals representative of the temperature detected by the thermal detectors, processes the group electric signals with reference to a group critical thermal event, identifies a critical group when the corresponding group electric signal detects the critical group thermal event, and generates group deactivating signals suitable for selectively deactivating the first and the at least one second junctions of the identified critical group with respect to the remaining junctions of the integrated circuit.
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公开(公告)号：US09606611B2
公开(公告)日：2017-03-28
申请号：US14591779
申请日：2015-01-07
Applicant: STMicroelectronics Application GmbH
Inventor： Fred Rennig
IPC: G06F1/26 , G06F1/32 , H04L12/403
CPC classification number: G06F1/3243 , G06F1/3209 , G06F1/3234 , G06F1/3287 , G06F1/3293 , H04L12/403 , Y02D10/10
Abstract: A bus microcontroller includes a processor circuit having at least one unit designed for performing one or more functions due to a bus command via a communication bus, a power control circuit adapted to be coupled to a transmitter-receiver circuit for receiving bus messages via the communication bus, and a means for placing at least part of the processor circuit into a reduced-power operating mode without placing the entire processor circuit into the reduced-power operating mode. The power control circuit is designed to evaluate incoming bus messages with respect to an activation bus message containing information on activating at least part of the processor circuit, and to output a corresponding activation control signal. The bus microcontroller also includes means for activating at least a part of the processor circuit that is placed in a reduced-power operating mode, in response to output of an activation control signal of the power control circuit.
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113.发明授权Battery comprising circuitry for charge and discharge control, and method of operating a battery 有权包括用于充电和放电控制的电路的电池以及操作电池的方法公开(公告)号：US08710801B2
公开(公告)日：2014-04-29
申请号：US13242649
申请日：2011-09-23
Applicant: Reiner Schwartz
Inventor： Reiner Schwartz
CPC classification number: H02J7/0026 , H02J7/0016 , H02J2007/0037 , H02J2007/004 , Y02T10/7055
Abstract: A battery includes a battery module that includes a plurality of submodules electrically connected in series. Each submodule comprises first and second submodule terminals and a cell. At least one submodule in each battery module is a switchable submodule comprising a submodule switching circuit. The submodule switching circuit is switchable between a first state and a second state. The submodule switching circuit electrically connects the cell of the switchable submodule between the first and second submodule terminals when the submodule switching circuit is in the first state. The submodule switching circuit provides an electrical bypass connection between the first and second submodule terminals and the cell of the switchable submodule is electrically disconnected from at least one of the first and second submodule terminals when the switching circuit is in the second state. The battery further comprises a control unit for operating the switching circuit of each module.
Abstract translation: 电池包括电池模块，其包括串联电连接的多个子模块。 每个子模块包括第一和第二子模块终端和一个单元。 每个电池模块中的至少一个子模块是包括子模块切换电路的可切换子模块。 子模块切换电路可在第一状态和第二状态之间切换。 当子模块切换电路处于第一状态时，子模块切换电路将可切换子模块的单元电连接在第一和第二子模块端子之间。 子模块切换电路在第一和第二子模块终端之间提供电旁路连接，并且当开关电路处于第二状态时，可切换子模块的单元与第一和第二子模块端子中的至少一个电气断开。 电池还包括用于操作每个模块的开关电路的控制单元。
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114.发明申请公开(公告)号：US20130214724A1
公开(公告)日：2013-08-22
申请号：US13849374
申请日：2013-03-22
Applicant: STMicroelectronics Application GmbH
Inventor： Reiner Schwartz
IPC: H02J7/00
CPC classification number: H02J7/0019 , B60L11/1866 , B60L2240/547 , B60L2240/549 , H02J7/0016 , Y02T10/7005 , Y02T10/7061
Abstract: A method and an active battery balancing circuit for balancing an electric charge in a plurality of cells of a battery that are electrically connected in series is disclosed. A first subset of the cells of the battery is electrically connected to an inductance for providing a current flow from the first subset through the inductance. The first subset of the cells is disconnected from the inductance, and a current is allowed to flow from the inductance into a second subset of the cells of the battery. At least one of the first and the second subset of the cells of the battery comprises two or more cells.
Abstract translation: 公开了一种用于平衡串联电连接的电池的多个单电池中的电荷的方法和有源电池平衡电路。 电池的单元的第一子集电连接到电感，以提供来自第一子集的电流流过电感。 电池的第一子集与电感断开，并且允许电流从电感流入电池单元的第二子集。 电池单元的第一和第二子集中的至少一个包括两个或更多个单元。
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公开(公告)号：US12259844B2
公开(公告)日：2025-03-25
申请号：US17829902
申请日：2022-06-01
Inventor： Giuseppe Cavallaro , Fred Rennig
IPC: G06F13/42 , G05B19/042 , G06F11/10 , G06F13/38 , G06F13/40
Abstract: In an embodiment a microcontroller includes a processing unit and a deserial-serial peripheral interface (DSPI) module, wherein the deserial-serial peripheral interface module is coupleable to a communication bus configured to operate according to a selected communication protocol, wherein the processing unit is configured to read user data intended for inclusion in an outgoing frame encoded according to the selected communication protocol, calculate, as a function of the user data, a cyclic redundancy check (CRC) value intended for inclusion in the outgoing frame, compose the outgoing frame by including the user data and the calculated CRC value into the outgoing frame, produce a DSPI frame encoded according to the selected communication protocol as a function of the outgoing frame and program a data register of the deserial-serial peripheral interface module with the DSPI frame, and wherein the deserial-serial peripheral interface module is configured to transmit the DSPI frame via the communication bus.
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Patent Agency Ranking
公开(公告)号：US12210609B2
公开(公告)日：2025-01-28
申请号：US17515149
申请日：2021-10-29
Inventor： Avneep Kumar Goyal , Thomas Szurmant
Abstract: A system on a chip including a first-port controller for a first development port configured to receive a first development tool and a second-port controller for a second development port configured to receive a second development tool. The system on a chip further including a central controller in communication with the first-port controller, the second-port controller, and a security subsystem. The central controller being configured to manage authentication exchanges between the security subsystem and the first development tool and authentication exchanges between the security subsystem and the second development tool.
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公开(公告)号：US12147209B2
公开(公告)日：2024-11-19
申请号：US17704675
申请日：2022-03-25
Inventor： Rosario Martorana , Mose' Alessandro Pernice , Roberto Colombo
IPC: G05B19/042
Abstract: A set of configuration memory locations store configuration data for a microcontroller unit. A hardware monitoring module is coupled by an interconnection bus to the configuration memory locations. The hardware monitoring module reads from an instruction memory a command including an address of a target memory location in the set of configuration memory locations. Data is read from the target memory location corresponding to the address read and a checksum value is computed as a function of the data that is read from the target memory location. The computed checksum value is then compared to a respective expected checksum value stored in a checksum storage unit. An alarm signal is triggered in response to a mismatch detected between the computed checksum value and the respective expected checksum value.
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118.发明公开公开(公告)号：US20240362176A1
公开(公告)日：2024-10-31
申请号：US18764940
申请日：2024-07-05
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G05B19/042 , G06F9/54 , G06F11/07 , G06F11/10 , G06F13/40 , G06F13/42 , H03M13/09 , H04L12/40 , H04L12/403
CPC classification number: G06F13/362 , G05B19/042 , G06F9/542 , G06F11/0739 , G06F11/0757 , G06F11/0772 , G06F11/1004 , G06F13/4068 , G06F13/4282 , H04L12/40006 , H04L12/40013 , H04L12/40078 , H04L12/403 , G05B2219/1215 , G05B2219/2231 , G05B2219/31179 , H03M13/09 , H04L2012/40215
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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公开(公告)号：US12019118B2
公开(公告)日：2024-06-25
申请号：US18186549
申请日：2023-03-20
Inventor： Roberto Colombo , Vivek Mohan Sharma , Samiksha Agarwal
IPC: G01R31/317
CPC classification number: G01R31/31703 , G01R31/31722
Abstract: In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.
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公开(公告)号：US20230409341A1
公开(公告)日：2023-12-21
申请号：US18312237
申请日：2023-05-04
Inventor： Asif Rashid Zargar , Roberto Colombo
IPC: G06F9/4401 , G06F21/64
CPC classification number: G06F9/4405 , G06F21/64
Abstract: In embodiments, a reset management circuit executes reset, configuration, and software runtime phases when a processing system is switched on, where one or more microprocessors start at respective start addresses. During the configuration phase, a circuit reads a boot record from a non-volatile memory and stores it to registers. The circuit sequentially reads data records of configuration data from the non-volatile memory and generates a write request for each data record to store the data of the respective data record to a second circuit with associated address data indicated in the respective data record. The processing system processes the boot record and boot configuration data provided by the second circuits to selectively start a predetermined microprocessor at a default start address or at a start address indicated by the boot configuration data, or start one or more microprocessors at respective start addresses as indicated by the boot record.
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