Abstract:
2 이상의 스레드로부터의 명령어를 동시에 실행하는 다중 스레드 프로세서(10)의 성능 특성을 모니터하는 방법과 장치가 개시된다. 이벤트 검출기는 다중 스레드 프로세서의 스레드들로부터의 명령어의 실행 중에 특정 프로세서 이벤트(20)의 발생을 검출한다. 특수 이벤트 선택 제어 레지스터(30)는 모니터될 이벤트의 선택, 마스킹 및 자격부여를 제어하도록 프로그램된다. 이벤트는 그들의 스레드 ID와 스레드 현재 특권 레벨(CPL)에 따라서 자격이 부여된다. 자격이 부여된 각 이벤트는 모니터되고 있는 모든 프로세서 이벤트를 기억하는 몇 개의 프로그래머블 이벤트 카운터(70) 중 하나에 의해 카운트된다. 그런 다음에, 이벤트 카운트의 내용은 프로그램 명령을 통해 액세스되고 샘플링될 수 있다.
Abstract:
PURPOSE: A speculative processor is manufactured to count a non-speculative event by counting the occurrence of a designated event, designating the event to be monitored, monitoring the designated event, generating the occurrence time value of the designated event and generating the number of times of occurrence of the designated event. CONSTITUTION: A system (200) is provided with a hierarchical memory (210) and a processor (250). Further, the hierarchical memory (210) is provided with a level (2) cache (212), a random access memory(RAM) (214) and a disk (216). Thus, a speculative processor is provided with plural counters for counting the occurrence of a designated event in a data processing system inside a performance monitor. The event to be monitored is designated. The designated event is monitored during the execution of an instruction due to the speculative processor. The number of times of occurrence of the designated event related to all the instructions to be executed by the speculative processor is generated and the number of times of occurrence related to the completely executed instruction is generated.
Abstract:
Instructions and logic provide user-level thread synchronization with MONITOR and MWAIT instructions. One or more model specific registers (MSRs) in a processor may be configured in a first execution state to specify support of a user-level thread synchronization architecture. Embodiments include multiple hardware threads or processing cores, corresponding monitored address state storage to store a last monitored address for each of a plurality of execution threads that issues a MONITOR request, cache memory to record MONITOR requests and associated states for addresses of memory storage locations, and responsive to receipt of an MWAIT request for the address, to record an associated wait-to-trigger state of monitored addresses for execution cores associated with an MWAIT request; wherein the execution core is to transition a requesting thread to an optimized sleep state responsive to the receipt of said MWAIT request when said one or more MSRs are configured in the first execution state.
Abstract:
A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.
Abstract:
A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.
Abstract:
Web conference performance monitoring systems enable presenters to monitor their audience's content receiving experience and modify their content's transmission characteristics to resolve technical difficulties. A system for monitoring a Web conference's performance includes a local processor; memory operably connected to the local processor; a monitor operably connected to the local processor; content loaded into memory and operable by the local processor; and an audience screen preview program loaded into the memory and operable by the local processor, wherein the audience screen preview program instructs the local processor to measure network throughput of a network connection between the local processor and a remote processor and display at least a portion of the content on the monitor operably connected to the local processor by simulating the content being transmitted to the monitor operably connected to the local processor over the network connection.
Abstract:
A data processing apparatus comprising a processor for executing a data processing process and a processor for executing a tuning process is disclosed. The data processing apparatus is arranged such that the tuning process which is a different process to the data processing process can access the parameters of speculative mechanisms of the data processing process and tune the parameters so that the mechanisms speculate differently and in this way the performance of this data processing process can be improved.