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    THERMAL THROTTLING OF ELECTRONIC DEVICES
    1.
    发明申请
    THERMAL THROTTLING OF ELECTRONIC DEVICES 审中-公开
    电子设备的热转折

    公开(公告)号：WO2016209348A1

    公开(公告)日：2016-12-29

    申请号：PCT/US2016/028849

    申请日：2016-04-22

    Applicant: INTEL CORPORATION

    Inventor： KAM, Timothy Y. ,  AHUJA, Sandeep ,  AGARWAL, Rajat ,  SODANI, Avinash ,  SUH, Jinho ,  CHINTHAMANI, Meenakshisundaram

    IPC: G06F1/20

    CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/16

    Abstract: Disclosed herein is a computing device configured to implement thermal throttling of a component of the computing device. The computing device includes an electronic component and a temperature sensor thermally coupled to the electronic component. The computing device also includes a thermal management controller to receive a temperature measurement from the temperature sensor and generate a throttling factor for the electronic component. If the temperature measurement is greater than a specified threshold, the throttling factor is to reduce performance of the electronic component to be at least the performance guarantee for the electronic component.

    Abstract translation: 这里公开了一种被配置为实现计算设备的部件的热调节的计算设备。 计算设备包括热耦合到电子部件的电子部件和温度传感器。 计算设备还包括热管理控制器，用于从温度传感器接收温度测量并产生电子部件的节流因子。 如果温度测量值大于指定的阈值，则节流因素是将电子元件的性能降至至少为电子元件的性能保证。

    MINIMIZING SNOOP TRAFFIC LOCALLY AND ACROSS CORES ON A CHIP MULTI-CORE FABRIC
    2.
    发明申请
    MINIMIZING SNOOP TRAFFIC LOCALLY AND ACROSS CORES ON A CHIP MULTI-CORE FABRIC 审中-公开
    在芯片多核心布料上最小化SNOOP交通本地和跨芯

    公开(公告)号：WO2017112192A1

    公开(公告)日：2017-06-29

    申请号：PCT/US2016/062926

    申请日：2016-11-18

    Applicant: INTEL CORPORATION

    Inventor： VINOD, Krishna N. ,  SODANI, Avinash ,  AURANGABADWALA, Zainulabedin J.

    IPC: G06F12/0811

    CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F2212/621

    Abstract: A processor includes a processing core, a L1 cache comprising a first processing core and a first L1 cache comprising a first L1 cache data entry of a plurality of L1 cache data entries to store data. The processor also includes an L2 cache comprising a first L2 cache data entry of a plurality of L2 cache data entries. The first L2 cache data entry corresponds to the first L1 cache data entry and each of the plurality of L2 cache data entries are associated with a corresponding presence bit (pbit) of a plurality of pbits. Each of the plurality of pbits indicates a status of a corresponding one of the plurality of L2 cache data entries. The processor also includes a cache controller, which in response to a first request among a plurality of requests to access the data at the first L1 cache data entry, determines that a copy of the data is stored in the first L2 cache data entry; and retrieves the copy of the data from the L2 cache data entry in view of the status of the pbit.

    Abstract translation: 处理器包括处理核心，包含第一处理核心的L1高速缓存以及包括用于存储数据的多个L1高速缓存数据条目的第一L1高速缓存数据条目的第一L1高速缓存。 处理器还包括L2高速缓存，其包括多个L2高速缓存数据条目的第一L2高速缓存数据条目。 第一L2高速缓存数据条目对应于第一L1高速缓存数据条目并且多个L2高速缓存数据条目中的每一个与多个pbit中的对应存在位（pbit）相关联。 多个pbit中的每一个指示多个L2高速缓存数据条目中对应的一个的状态。 处理器还包括高速缓存控制器，其响应于在第一L1高速缓存数据条目处访问数据的多个请求中的第一请求，确定数据的副本被存储在第一L2高速缓存数据条目中; 并根据pbit的状态从L2高速缓存数据条目中检索数据的副本。

    METHOD AND APPARATUS FOR USER-LEVEL THREAD SYNCHRONIZATION WITH A MONITOR AND MWAIT ARCHITECTURE
    3.
    发明申请
    METHOD AND APPARATUS FOR USER-LEVEL THREAD SYNCHRONIZATION WITH A MONITOR AND MWAIT ARCHITECTURE 审中-公开
    使用监视器和MWAIT体系结构进行用户级线程同步的方法和设备

    公开(公告)号：WO2017112374A1

    公开(公告)日：2017-06-29

    申请号：PCT/US2016/064114

    申请日：2016-11-30

    Applicant: INTEL CORPORATION

    Inventor： CHAFFIN, Benjamin C. ,  KYANKO, Robert J. ,  SODANI, Avinash

    IPC: G06F9/30 ,  G06F12/02 ,  G06F12/0811

    CPC classification number: G06F9/52 ,  G06F12/0806 ,  G06F2201/885 ,  G06F2209/521

    Abstract: Instructions and logic provide user-level thread synchronization with MONITOR and MWAIT instructions. One or more model specific registers (MSRs) in a processor may be configured in a first execution state to specify support of a user-level thread synchronization architecture. Embodiments include multiple hardware threads or processing cores, corresponding monitored address state storage to store a last monitored address for each of a plurality of execution threads that issues a MONITOR request, cache memory to record MONITOR requests and associated states for addresses of memory storage locations, and responsive to receipt of an MWAIT request for the address, to record an associated wait-to-trigger state of monitored addresses for execution cores associated with an MWAIT request; wherein the execution core is to transition a requesting thread to an optimized sleep state responsive to the receipt of said MWAIT request when said one or more MSRs are configured in the first execution state.

    Abstract translation:

    指令和逻辑提供用户级线程与MONITOR和MWAIT指令的同步。 处理器中的一个或多个模型特定寄存器（MSR）可以被配置为处于第一执行状态以指定对用户级线程同步体系结构的支持。 实施例包括多个硬件线程或处理核心，对应的监视地址状态存储器，用于存储发出MONITOR请求的多个执行线程中的每个执行线程的最后监视地址，用于记录MONITOR请求的存储器以及用于存储器存储位置的地址的关联状态， 以及响应于接收到针对该地址的MWAIT请求，记录与MWAIT请求相关联的执行核心的监视地址的相关联的等待触发状态; 其中，当所述一个或多个MSR被配置在所述第一执行状态时，所述执行核心响应于所述MWAIT请求的接收而将请求线程转变为优化的睡眠状态。

    PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION
    4.
    发明申请
    PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
    具有分支机构错误预测的第二个执行单元的处理程序

    公开(公告)号：WO2013100998A1

    公开(公告)日：2013-07-04

    申请号：PCT/US2011/067656

    申请日：2011-12-28

    Applicant: INTEL CORPORATION ,  MERTEN, Matthew, C. ,  SODANI, Avinash ,  MIRKES, Sean, P. ,  KADGI, Vijaykumar, B. ,  SUTANTO, Bambang ,  LAI, Chia Yin, Kevin ,  MARDEN, Morris ,  FARCY, Alexandre, J.

    Inventor： MERTEN, Matthew, C. ,  SODANI, Avinash ,  MIRKES, Sean, P. ,  KADGI, Vijaykumar, B. ,  SUTANTO, Bambang ,  LAI, Chia Yin, Kevin ,  MARDEN, Morris ,  FARCY, Alexandre, J.

    IPC: G06F1/00 ,  G06F9/30 ,  G06F9/46

    CPC classification number: G06F9/3844 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

    Abstract: A secondary jump execution unit (JEU) is incorporated in a micro-processor to operate concurrently with a primary JEU, enabling the execution of simultaneous branch operations with possible detection of multiple branch mispredicts. When branch operations are executed on both JEUs in a same instruction cycle, mispredict processing for the secondary JEU is skidded into the primary JEU's dispatch pipeline such that the branch processing for the secondary JEU occurs after processing of the branch for the primary JEU and while the primary JEU is not processing a branch. Moreover, in cases when a nuke command is also received from a reorder buffer of the processor, the branch processing for the secondary JEU is further delayed to accommodate processing of the nuke on the primary JEU. Further embodiments support the promotion of the secondary JEU to have access to the mispredict mechanisms of the primary JEU in certain circumstances.

    Abstract translation: 次级跳转执行单元（JEU）并入微处理器以与主JEU同时操作，使得能够执行同时分支操作，并可能检测到多个分支错误预测。 当在同一个指令周期中对两个JEU执行分支操作时，辅助JEU的错误预测处理被划分到主JEU的调度流水线中，使得辅助JEU的分支处理在主JEU的分支处理之后发生，而 初级JEU不处理分支。 此外，在从处理器的重新排序缓冲器接收到nuke命令的情况下，进一步延迟用于辅助JEU的分支处理，以适应主JEU上的nuke的处理。 进一步的实施方案支持促进联合联合国次级方案在某些情况下获得主要联合执行机构的错误预测机制。

    METHOD AND APPARATUS FOR USER-LEVEL THREAD SYNCHRONIZATION WITH A MONITOR AND MWAIT ARCHITECTURE
    6.
    发明公开
    METHOD AND APPARATUS FOR USER-LEVEL THREAD SYNCHRONIZATION WITH A MONITOR AND MWAIT ARCHITECTURE 审中-公开

    公开(公告)号：EP3394732A1

    公开(公告)日：2018-10-31

    申请号：EP16879845.2

    申请日：2016-11-30

    Applicant: Intel Corporation

    Inventor： CHAFFIN, Benjamin C. ,  KYANKO, Robert J. ,  SODANI, Avinash

    IPC: G06F9/30 ,  G06F12/02 ,  G06F12/0811

    CPC classification number: G06F9/52 ,  G06F12/0806 ,  G06F2201/885 ,  G06F2209/521

    Abstract: Instructions and logic provide user-level thread synchronization with MONITOR and MWAIT instructions. One or more model specific registers (MSRs) in a processor may be configured in a first execution state to specify support of a user-level thread synchronization architecture. Embodiments include multiple hardware threads or processing cores, corresponding monitored address state storage to store a last monitored address for each of a plurality of execution threads that issues a MONITOR request, cache memory to record MONITOR requests and associated states for addresses of memory storage locations, and responsive to receipt of an MWAIT request for the address, to record an associated wait-to-trigger state of monitored addresses for execution cores associated with an MWAIT request; wherein the execution core is to transition a requesting thread to an optimized sleep state responsive to the receipt of said MWAIT request when said one or more MSRs are configured in the first execution state.

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