公开(公告)号：WO1983001858A1

公开(公告)日：1983-05-26

申请号：PCT/US1982000383

申请日：1982-04-26

Applicant: DMA SYSTEMS CORPORATION

Inventor： DMA SYSTEMS CORPORATION ,  LEWIS, Martyn, A. ,  PENNIMAN, Steven, K. ,  SUTTON, David, A.

IPC: G11B05/09

CPC classification number: G11B5/59655

Abstract: Dans un système de stockage à disque magnétique et un disque magnétique utilisé dans ce système, le disque possède des surfaces opposées, au moins l'une d'elles étant recouverte d'un matériau magnétique, le disque est monté sur une broche de manière à tourner par rapport à un transducteur magnétique positionné pour l'enregistrement et la lecture de données sur le disque, une pluralité de pistes annulaires concentriques sont définies à la surface du disque, chacune des pistes étant divisée en une pluralité de secteurs, à chacun desquels sont associées des servo-données préenregistrées pour son identification. Les servo-données pour chaque secteur comprennent un code d'identification de piste à distance unitaire (14) enregistrée trois fois de suite, le code étant variable entre des secteurs adjacents de pistes adjacentes, et un code de contrôle à décalage d'horloge (15) est enregistré immédiatement à la suite du dernier code d'identification de piste enregistré, le même code de contrôle à décalage d'horloge étant enregistré pour chaque secteur de chaque piste.

公开(公告)号：WO1983001334A1

公开(公告)日：1983-04-14

申请号：PCT/US1982001428

申请日：1982-10-04

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  RUBINSON, Barry, L. ,  PARENTI, Mark, A. ,  LARY, Richard, F. ,  GARDNER, Edward, A.

IPC: G11B05/09

CPC classification number: G11B20/1883 ,  G11B20/1252 ,  G11B20/1803 ,  G11B2220/20 ,  G11B2220/2508

Abstract: Format de disque qui améliore la gestion de segments défectueux d'un support et réduit le temps d'accès dans une unité de stockage de masse du type à disque pour des systèmes de traitement de données. Le format présente trois couches. Une première couche physique comprend les bytes, les secteurs et les ensembles de secteurs, ainsi que les codes de détection et de correction d'erreurs. Une deuxième couche logique est utilisée pour adresser la couche physique et pour recueillir des secteurs pour former une multiplicité d'espaces adressables séparément, avec un espace ayant une utilité fonctionnelle distincte. Dans la troisième couche fonctionnelle on spécifie l'utilisation de champs de données dans chaque espace. Cette couche régit en cas de besoin la gestion des blocs incorrects et l'utilisation de certaines informations de formats. Dans la couche physique, les bytes sont recueillis en secteurs, les secteurs sont recueillis en pistes, les pistes sont recueillies en groupes et les groupes en cylindres. Ces ensembles sont définis logiquement plutôt que physiquement. Un groupe est composé de pistes et les pistes individuelles d'un groupe peuvent être sélectionnées pendant le temps de rotation inter-secteur. Dans la couche logique, le disque est divisé en trois zones principales, chacune adressable séparément. La première zone principale est divisée en deux sous-zones. La première sous-zone (12) est accessible au système de calcul principal; la deuxième sous-zone (14 et 16) est utilisée pour le remplacement des blocs incorrects. La deuxième zone principale sert aux informations de formats. La troisième zone principale (18) sert au diagnostic. La gestion des blocs incorrects est contrôlée par un procédé à couches hiérarchiques. Une partie de chaque disque, distribuée au travers du milieu, est réservée à des secteurs d'apoints pour le remplacement de secteurs défectueux. Après le remplacement d'un secteur incorrect, toute tentative ultérieure d'accéder au secteur incorrect est adressée de nouveau (c'est-à-dire par

公开(公告)号：WO1980002341A1

公开(公告)日：1980-10-30

申请号：PCT/US1980000272

申请日：1980-03-17

Applicant: WESTERN ELECTRIC CO INC

Inventor： WESTERN ELECTRIC CO INC ,  MATTES H

IPC: G11B05/09

CPC classification number: G11B20/1419 ,  G06K7/016

Abstract: For the purpose of enabling proper card writing, and eventual reading, of a card moved by hand (and thus at a non-predictable rate) through a card writer, a rate adaptive magnetic card writer is provided which determines (10, 20, 22) the rate of movement of the card through the writer, and then uses the determined rate to control (24, 26, 30) the rate at which the data to be entered onto the card is written (15) thereon. The written data is thereby dispersed on the card enabling subsequent reading by a card reader.

Abstract translation: 为了能够通过卡写入器手动移动卡（因此以不可预测的速率）进行适当的卡写入和最终读取，提供了速率自适应磁卡写入器，其确定（10,20,22） ）卡通过写入器的移动速率，然后使用确定的速率来控制（24,26,30）在其上写入要输入到卡上的数据的速率（15）。 因此，写入的数据被分散在卡上，从而能够由读卡器进行后续读取。

公开(公告)号：EP0118121A3

公开(公告)日：1988-07-27

申请号：EP84102240

申请日：1984-03-02

Applicant: Research Corporation

Inventor： Titchener, Mark Renfreu

IPC: H04L07/04 ,  G11B05/09 ,  H03M07/42

CPC classification number: G11B20/1426 ,  H04L7/04

Abstract: The specification discloses a method and apparatus for' encoding and decoding a variable length augmented code for use in the transmission of sequential information as an indefinite length string of data. Both binary and alternate character code sets are discussed for transmitting and translating information. The variable length code symbols are self synchronizing, and will automatically reestablish synchronization within two characters if a bit or number of bits is lost through noise or faulty transmission. The resynchronization is automatic and occurs by virtue of the construction of the variable length augmented codes. In addition, a method and means of creating a fixed length depleted code for use in digital processors and digital storage media is also disclosed. Inasmuch as most digital processors utilize fixed length words, it is desirable to be able to convert the variable length augmented code into a fixed length depleted code, and to be able to reconvert from the depleted code back to the augmented code without necessity of resorting to an extensive lookup table for each of the characters. In creating the augmented set of self synchronizing variable length code symbols, the original character set C° is augmented 9 times until the C q = 2 q (n-1) +1 wherein n represents the number of distinct elements in the original character set C° that was augmented, and C q is equal to the number of symbols derived in the final augmented set C q , and is equal to or greater than the desired number of characters to be used in the data handling and communication.

公开(公告)号：EP0117756A3

公开(公告)日：1987-08-19

申请号：EP84301277

申请日：1984-02-27

Applicant: NEC CORPORATION

Inventor： Kaneko, Takashi

IPC: G11B05/09 ,  G06F11/10 ,  H04L01/10

CPC classification number: G11B20/1876

Abstract: The circuit (21) implements a known interpolation algorithm processing words flagged (F n , F n+1 ) as in error or correct. A correct word is passed on unchanged. An incorrect word is replaced by the means of the most recent correct word and the ensuing word, if that be correct, whereas it is replaced by the most recent correct word if the ensuing word is also incorrect. In order to avoid the complexity of known circuits with multiple latches and a complex output multiplexer, the words are written selectively into two address locations (a, β) in a RAM 15 in such a way that an adder 16 is always able to furnish the desired result to an output latch (17).

公开(公告)号：EP0117287A3

公开(公告)日：1987-02-25

申请号：EP83111128

申请日：1983-11-08

Applicant: International Business Machines Corporation

Inventor： Patel, Arvind Motibhai

IPC: G11B05/09 ,  G06F11/10 ,  H04L01/10

CPC classification number: G11B20/1809 ,  H03M13/15

Abstract: A two-level multibyte error correcting system for correcting up to t, one-byte errors in a codeword in response to processing 2t, non-zero syndrome bytes at the first level and up to t 2 one-byte errors in a codeword in response to processing 2t 2 non-zero syndrome bytes at the second level when processing said 2t, syndrome bytes at said first level does not produce an all zero pattern for said 2t 2 syndrome bytes. The system is particularly applicable to data handling devices such as disk files, where in a relatively long block of data may be divided into subblocks, each of which may contain up to t, - x one-byte errors that are correctable at the first level by processing 2t, non-zero syndrome bytes. One identifiable subblock of the word may contain up to t, + x one-byte errors which are correctable by processing said 2t 2 non-zero syndrome bytes where 0 ≤ x 2 - t 1 ).

公开(公告)号：EP0112988A3

公开(公告)日：1987-02-04

申请号：EP83110500

申请日：1983-10-21

Applicant: International Business Machines Corporation

Inventor： Patel, Arvind Motibhai

IPC: G06F11/10 ,  G11B05/09 ,  H04L01/10

CPC classification number: H03M13/151 ,  G11B20/1833

Abstract: A syndrome processing unit for a multibyte error correcting system includes logical circuitry for performing product operation on selected pairs of 8-bit syndrome bytes, and exclusive-OR operations on selected results of the product operations are selectively combined to define usable cofactors that correspond to coefficients of the error locator polynomial if the codeword contains less than the maximum number of errors for which the system has been designed.

公开(公告)号：EP0117753A3

公开(公告)日：1986-12-17

申请号：EP84301270

申请日：1984-02-27

Applicant: SONY CORPORATION

Inventor： Omori, Takashi c/o Patent Division ,  Sugiki, Hiraku c/o Patent Division

IPC: G11B05/58 ,  G11B05/09 ,  G11B15/46

CPC classification number: G11B15/4677 ,  G11B5/588 ,  G11B5/5921

Abstract: In a system for recording and reproducing digital signals on a magnetic tape (12) using a rotary head (11 A, 11 B), in which the signals are recorded as a series of slanted tracks (14A, 14B) without guard bands between adjacent tracks (14A, 14B), a pilot signal that was recorded during the recording process is used to control the tracking of the playback head (11 A, 11 B). The pilot signal is recorded at a specific position in a specific pilot signal record region, independent from the region of the track (14A, 14B) at which the information signal is recorded, and the pilot signal is arranged at a predetermined position or positions being a specified distance from an end of each track (14A, 14B) in its longitudinal direction, and only alternate tracks receive the pilot signal. When the recorded tracks (14A, 14B) are reproduced by a rotary playback (11 A, 11 B) having a tracing width that is greater than the width of the track (14A, 14B), the pilot signals from the adjacent tracks (14A, 14B) will be detected and can be compared in level, with the comparison output being used to control the tracking of the rotary playback head (11 A, 11 B).

公开(公告)号：EP0109248A3

公开(公告)日：1986-08-13

申请号：EP83306794

申请日：1983-11-08

Applicant: FUJITSU LIMITED

Inventor： Uno, Hiroshi

IPC: G11B05/09 ,  G11B20/10

CPC classification number: G11B20/10194 ,  G11B20/10212

Abstract: 57 A write data compensating circuit in a magnetic recorder comprises a shifting circuit (40) for shifting binary data (Din) in time relation and for producing front, present, and rear signals related to the binary data, and a combination logic circuit (50) for applying a preshift to the present signal provided as write data in accordance with a pattern of the front, present, and rear signals. The combination logic circuit comprises a first circuit (51-55) which is operative to detect the pitch of each two adjacent inversions of magnetization to be created by the write data, and a second circuit (58-63) operative to adjust each pulse width of the write data on the basis of an analysis by the first circuit.

公开(公告)号：EP0094671A3

公开(公告)日：1986-07-16

申请号：EP83104820

申请日：1983-05-16

Applicant: SONY CORPORATION

Inventor： Odaka, Kentaro ,  Sako, Yoichiro ,  Kojima, Yuichi ,  Nakano, Kenji ,  Moriwaki, Hisayoshi

IPC: G11B05/09 ,  H04L01/10 ,  G06F11/10

CPC classification number: G11B20/1809

Abstract: In the recording/reproducing of digital audio signals, errors are detected and corrected by using two parity words, one arranged at the center of the block formed of data words and the arranged at one end of the block. The probability that uncorrectable error will be present in the center of the block is relatively high, so placing the parity word there prevents loss of the more valuable data. Maximum correctable burst errors are determined by the length of the block, so placing the other parity word on the end of the block lengthens it and improves burst error correction. The parity words are arranged as indicated before adding a cyclic redundancy check (CRC) code to the data signal and then modulation coding the signal before recording. During playback, the reproduced signal is demodulated and the CRC code used to detect errors for which error pointers are generated. The reproduced data is read into memories (3,4) in accordance with generated addresses and the pointers prevent the writing in of words found to be in error, which error words are subsequently corrected if possible using parity codes originally encoded into the signals prior to recording.