公开(公告)号：US20180375470A1

公开(公告)日：2018-12-27

申请号：US16013917

申请日：2018-06-20

Applicant: CHROMA ATE INC.

Inventor： Cheng-Ting TSAI ,  Lan-Sheng YANG

IPC: H02S50/10 ,  G02B27/30 ,  H01L31/0224 ,  H01L31/048

CPC classification number: H02S50/10 ,  G02B27/30 ,  H01L31/022425 ,  H01L31/048 ,  H02S50/15

Abstract: A method for inspecting a solar cell and configured to inspect a peeling state of a three-dimensional pattern of the solar cell includes obliquely illuminating the three-dimensional pattern of the solar cell using a light beam. An image of the solar cell is normally captured. An intensity of the light beam is increased to increase a contrast between the three-dimensional pattern and a shadow of the three-dimensional pattern in the image and increase a contrast between an ink pattern of the solar cell and the shadow in the image to overexpose the ink pattern in the image. Determine if the three-dimensional pattern is peeling according to the shadow of the three-dimensional pattern in the image.

公开(公告)号：US20180323481A1

公开(公告)日：2018-11-08

申请号：US15912222

申请日：2018-03-05

Applicant: CHROMA ATE INC.

Inventor： Chih-Ming TSAI ,  Chao-Hsu CHEN ,  Han-Chou LIAO ,  Chung-Yu SIANG

IPC: H01M10/48 ,  H01M10/44 ,  G01R19/165 ,  H01M10/42

Abstract: A method is provided for testing a semi-finished battery cell. The semi-finished battery cell is charged with a constant current when a voltage difference between the first conductor and the second conductor is less than a voltage threshold. The semi-finished battery cell is charged with a constant voltage when the voltage difference between the first conductor and the second conductor is equal to or larger than the voltage threshold. An overall electric quantity is obtained after a default time period, wherein the overall electric quantity is an electric quantity charged to the semi-finished battery cell with the constant current during the default time period. Accordingly, an insulation related to electrodes of the semi-finished battery cell is determined as poor when the overall electric quantity is larger than an electric quantity threshold.

公开(公告)号：US10034410B1

公开(公告)日：2018-07-24

申请号：US15497231

申请日：2017-04-26

Applicant: CHROMA ATE INC.

Inventor： Sheng-Chin Chuang ,  Kuei-Wen Lien ,  Chung-Lin Liu ,  Ming-Ju Chuang ,  Hsiu-Wei Kuo ,  Ming-Hui Wang ,  Chih-Hsien Wang

IPC: H05K7/20 ,  H05K5/02

Abstract: A support apparatus is configured to support electronic components. The support apparatus includes a tray and a plurality of recessed structures. The tray has a cavity therein and at least one intake hole communicated with the cavity. The recessed structures are disposed on the tray and recessed toward the cavity. Each of the recessed structures is configured to accommodate at least a part of a corresponding one of the electronic components and includes a support surface and a plurality of first spacers. The support surface has an exhaust hole communicated with the cavity. The first spacers are disposed on the support surface of a corresponding one of the recessed structures. When a corresponding one of the electronic components is supported on the first spacers, any adjacent two of the first spacers and the corresponding electronic component form a first flow channel.

公开(公告)号：US09954255B2

公开(公告)日：2018-04-24

申请号：US14884822

申请日：2015-10-16

Applicant: CHROMA ATE INC.

Inventor： James E. Hopkins

IPC: H01M10/48 ,  H01M10/42 ,  G01B21/32 ,  H01M2/10

CPC classification number: H01M10/48 ,  G01B21/32 ,  H01M2/1061 ,  H01M10/4285 ,  H01M2220/30

Abstract: A measurement fixture for a battery cell is provided when the battery cell is connected to an apparatus. The measurement fixture comprises a chamber, a pressure sensor and an expansion sensor. The chamber defines a sealed space for receiving the battery cell. The pressure sensor is mounted to the chamber to sense a change of pressure in the sealed space due to a volume change of the battery cell to calculate pressure in the battery cell and the volume change of the battery cell non-contactly. The expansion sensor is mounted to the chamber to sense a deformation of the battery cell to calculate a correlation between the pressure in the battery cell and the volume change of the battery cell non-contactly.

公开(公告)号：US09841737B2

公开(公告)日：2017-12-12

申请号：US14961535

申请日：2015-12-07

Applicant: CHROMA ATE INC.

Inventor： Chih-Cherng Lu ,  Chia-Ching Ting ,  Chuan-Tse Lin

IPC: G05B11/01 ,  G01R31/28 ,  G01R31/36 ,  G01R35/00 ,  G01R31/319

CPC classification number: G05B11/01 ,  G01R31/2834 ,  G01R31/3191 ,  G01R31/3641 ,  G01R35/00 ,  G01R35/005

Abstract: An automatic test system and method are provided. The automatic test system includes at least one formation apparatus and a test fixture. The formation apparatus receives a first control command from a network and executes a test procedure according to the first control command. The test procedure includes a charging mode and a discharging mode. The test fixture is selectively coupled to the formation apparatus. During the test procedure, when the test fixture is coupled to the formation apparatus, the test fixture generates a first measurement result. The test fixture transmits the first measurement result to the formation apparatus via a wireless communication interface of the test fixture.

公开(公告)号：US09678158B2

公开(公告)日：2017-06-13

申请号：US14644552

申请日：2015-03-11

Applicant: CHROMA ATE INC.

Inventor： Chien-Ming Chen

IPC: G01R31/00 ,  G01R31/3185 ,  G01R31/28 ,  G01R1/04

CPC classification number: G01R31/318513 ,  G01R1/04 ,  G01R31/2863

Abstract: An apparatus for testing a package-on-package semiconductor device includes a top cover, a lower base, a heat dissipation module, and a plurality of probes. The lower base is disposed under the top cover so as to form an internal accommodation space for receiving an upper chip. The heat dissipation module includes a heat sink arranged in the internal accommodation space and attached to an upper surface of the upper chip. The probes are arranged in the lower base so as to electrically connect the upper chip with a lower chip. By the heat sink arranged in the internal accommodation space formed of the top cover and the lower base, heat generated from the upper chip during operation of the upper chip can be greatly dissipated so that the performance and the service life of the upper chip can be improved.

公开(公告)号：US20170045552A1

公开(公告)日：2017-02-16

申请号：US15195794

申请日：2016-06-28

Applicant: CHROMA ATE INC.

Inventor： Mao-Sheng LIU ,  Hsiu-Wei KUO ,  Chao-Hsu CHEN

IPC: G01R1/067 ,  G01R31/36

CPC classification number: G01R1/06788 ,  G01R1/06738 ,  G01R31/364

Abstract: A probe includes a first electrical conductor, a second electrical conductor and a voltage measurer. The first electrical conductor has a first through hole, and the first through hole extends through two ends of the first electrical conductor. The second electrical conductor is detachably disposed on the first electrical conductor, and the second electrical conductor has a working surface and a second through hole. The working surface is located at an end of the second electrical conductor away from the first electrical conductor. Two ends of the second through hole that are opposite to each other are located at the working surface and an end of the first through hole, respectively. The first through hole is communicated with the second through hole. The voltage measurer is penetrating through the first through hole and the second through hole.

Abstract translation: 探头包括第一电导体，第二电导体和电压测量器。 第一电导体具有第一通孔，第一通孔延伸穿过第一电导体的两端。 第二电导体可拆卸地设置在第一电导体上，第二电导体具有工作表面和第二通孔。 工作表面位于第二电导体远离第一电导体的一端。 彼此相对的第二通孔的两端分别位于工作表面和第一通孔的端部。 第一通孔与第二通孔连通。 电压测量器穿过第一通孔和第二通孔。

公开(公告)号：US09347989B2

公开(公告)日：2016-05-24

申请号：US13875660

申请日：2013-05-02

Applicant: CHROMA ATE INC.

Inventor： Chien-Ming Chen ,  Meng-Kung Lu

IPC: G01R31/00 ,  G01R31/28

CPC classification number: G01R31/2887 ,  G01R31/2896

Abstract: A test device is provided for testing a bottom chip of a package-on-package (PoP) stacked-chip. An upper surface of the bottom chip has a plurality of soldering points for electrically connecting a plurality of corresponding soldering points of a top chip of the PoP stacked-chip. The test device includes a test head and a plurality of test contacts. The test head has the top chip installed inside. The plurality of test contacts is installed on a lower surface of the test head and electrically connected to the plurality of corresponding soldering points of the top chip inside the test head. When the lower surface of the test head contacts the upper surface of the bottom chip, the plurality of test contacts is electrically connected to the plurality of soldering points for testing the bottom chip.

Abstract translation: 提供了一种用于测试封装封装（PoP）堆叠芯片的底部芯片的测试设备。 底部芯片的上表面具有用于电连接PoP堆叠芯片的顶部芯片的多个对应焊接点的多个焊接点。 测试装置包括测试头和多个测试触点。 测试头内部安装了顶部芯片。 多个测试触点安装在测试头的下表面上并电连接到测试头内的顶部芯片的多个对应焊接点。 当测试头的下表面接触底部芯片的上表面时，多个测试触点电连接到多个焊接点以测试底部芯片。

公开(公告)号：US20150323257A1

公开(公告)日：2015-11-12

申请号：US14681093

申请日：2015-04-08

Applicant: CHROMA ATE INC.

Inventor： Hsiu-Wei KUO ,  Xin-Yi WU ,  Ben-Mou YU ,  Ming-Chang WU ,  Mao-Sheng LIU ,  Kuei-Wen LIEN

IPC: F27D7/04 ,  F27D5/00 ,  F27B1/08

CPC classification number: F27B1/08 ,  F27B17/0083 ,  F27D7/04 ,  F27D2007/045

Abstract: The disclosure discloses a heating furnace including a housing, a first rack, a chamber, and at least one fan. The first rack is disposed in the housing. The chamber is disposed in the housing and located at a side of the first rack. The chamber includes an inlet, a first sidewall, and a second sidewall. The first sidewall is adjacent to the first rack. The first sidewall has a plurality of vents. The first sidewall and the second sidewall are disposed to face each other. A width is spaced between the first sidewall and the second sidewall, and the width is larger than or equal to 200 mm. The fan is disposed in the housing for generating an airflow to the inlet.

Abstract translation: 本公开公开了一种加热炉，其包括壳体，第一齿条，腔室和至少一个风扇。 第一个机架设置在外壳中。 腔室设置在壳体中并且位于第一齿条的一侧。 腔室包括入口，第一侧壁和第二侧壁。 第一侧壁与第一机架相邻。 第一侧壁具有多个通风孔。 第一侧壁和第二侧壁被设置为彼此面对。 宽度在第一侧壁和第二侧壁之间间隔开，并且宽度大于或等于200mm。 风扇设置在壳体中以产生到入口的气流。

公开(公告)号：US20150260793A1

公开(公告)日：2015-09-17

申请号：US14644552

申请日：2015-03-11

Applicant: CHROMA ATE INC.

Inventor： Chien-Ming CHEN

IPC: G01R31/319 ,  G01R1/04

CPC classification number: G01R31/318513 ,  G01R1/04 ,  G01R31/2863

Abstract: An apparatus for testing a package-on-package semiconductor device includes a top cover, a lower base, a heat dissipation module, and a plurality of probes. The lower base is disposed under the top cover so as to form an internal accommodation space for receiving an upper chip. The heat dissipation module includes a heat sink arranged in the internal accommodation space and attached to an upper surface of the upper chip. The probes are arranged in the lower base so as to electrically connect the upper chip with a lower chip. By the heat sink arranged in the internal accommodation space formed of the top cover and the lower base, heat generated from the upper chip during operation of the upper chip can be greatly dissipated so that the performance and the service life of the upper chip can be improved.

Abstract translation: 一种用于测试封装封装半导体器件的装置，包括顶盖，下基座，散热模块和多个探针。 下基部设置在顶盖下方，以形成用于容纳上芯片的内部容纳空间。 散热模块包括布置在内部容纳空间中并连接到上部芯片的上表面的散热器。 探针布置在下基座中，以便将上芯片与下芯片电连接。 通过布置在由顶盖和下基座形成的内部容置空间中的散热器，可以大大消耗从上芯片操作期间从上芯片产生的热量，使得上芯片的性能和使用寿命可以 改进。