公开(公告)号：WO2015200132A1

公开(公告)日：2015-12-30

申请号：PCT/US2015/036701

申请日：2015-06-19

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： MEDNIK, Alexander ,  TIRUMALA, Rohit ,  TAN, Mark ,  KRUGLY, Simon

IPC: H02H3/04 ,  H02H3/08 ,  H02H3/093

CPC classification number: G01R31/2621 ,  G01R31/025 ,  H02H3/044 ,  H02H3/08 ,  H02H3/093

Abstract: A circuit and method are provided detecting a persistent short circuit in a power MOSFET for the purpose of protecting a load from over-current. The method determining a fault condition in a circuit comprising a switch provided with a gate, a first terminal and a second terminal, the first terminal being coupled to a load and the second terminal being coupled to a current sense element, and after a blanking delay, comparing a voltage at the current sense element with a reference voltage and asserting a signal indicating a fault condition if the voltage at the current sense element exceeds the reference voltage.

Abstract translation: 提供了检测功率MOSFET中的持续短路以便保护负载免受过电流的电路和方法。 该方法确定电路中的故障状态，该电路包括设置有门，第一端子和第二端子的开关，第一端子耦合到负载，第二端子耦合到电流感测元件，以及在消隐延迟之后 将电流检测元件上的电压与参考电压进行比较，并且如果电流检测元件上的电压超过参考电压，则断言指示故障状态的信号。

公开(公告)号：WO2013188059A1

公开(公告)日：2013-12-19

申请号：PCT/US2013/041818

申请日：2013-06-12

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： AKKIHAL, Shivanand, I. ,  MUELLER, Rainer

IPC: H04J3/06 ,  H04N21/43

CPC classification number: H04J3/0638 ,  H04J3/0647 ,  H04J3/0673

Abstract: A communication system and method is provided herein for synchronizing a plurality of network nodes after a network lock condition occurs within a network. According to one embodiment, the method may generate a local trigger signal simultaneously at each of the plurality of network nodes by compensating for unique phase delays attributed to each of the plurality of network nodes. As described herein, the local trigger signals may be used for synchronizing devices, such as multimedia devices, which may be coupled to the network nodes. More specifically, the local trigger signals may be used to synchronize events occurring within devices, which are coupled to different nodes of the network.

Abstract translation: 本文提供了一种在网络中发生网络锁定状况之后同步多个网络节点的通信系统和方法。 根据一个实施例，该方法可以通过补偿归因于多个网络节点中的每一个的唯一相位延迟来在多个网络节点中的每一个处同时生成本地触发信号。 如本文所述，本地触发信号可以用于同步诸如多媒体设备的设备，其可以耦合到网络节点。 更具体地，本地触发信号可以用于同步在耦合到网络的不同节点的设备内发生的事件。

公开(公告)号：WO1997045870A1

公开(公告)日：1997-12-04

申请号：PCT/US1997007243

申请日：1997-04-11

Applicant: MICROCHIP TECHNOLOGY, INC.

Inventor： MICROCHIP TECHNOLOGY, INC. ,  FINK, Scott ,  BINGHAM, Gregory ,  HULL, Richard ,  ELLISON, Scott

IPC: H01L23/48

CPC classification number: G06F13/40 ,  G06F15/7832 ,  G06F15/7867 ,  G11C5/066

Abstract: An Integrated Circuit (IC) (10) package is disclosed comprising an IC chip (11) with a microcontroller (12) therein having an n-bit data bus, and up to n pins (34-38) electrically coupled to the microcontroller (12). The IC package also includes a control register coupled to the microcontroller for receiving enable and disable signals from the microcontroller. One or more of the pins have one or more functional blocks associated thereto. Each functional block defines a specified function for its corresponding pin. Thus, each pin having a plurality of corresponding functional blocks has a number of potential functions equal to the number of corresponding functional blocks. The specific function for a given pin is selected by the enable signal from the control register which selects the appropriate functional block upon appropriate command from the microcontroller. By using pins with multiple functions, the instant invention permits an n-bit architecture microcontroller to use less than or up to n pins.

Abstract translation: 公开了一种集成电路（IC）（10）封装，其包括其中具有n位数据总线的微控制器（12）的IC芯片（11），以及电连接到微控制器的多达n个引脚（34-38） 12）。 IC封装还包括耦合到微控制器的控制寄存器，用于接收来自微控制器的使能和禁止信号。 一个或多个销具有与其相关联的一个或多个功能块。 每个功能块为其相应的引脚定义一个指定的功能。 因此，具有多个对应功能块的每个引脚具有等于相应功能块数量的多个潜在功能。 给定引脚的具体功能由来自控制寄存器的使能信号选择，该控制寄存器根据微控制器的适当命令选择适当的功能块。 通过使用具有多个功能的引脚，本发明允许n位架构微控制器使用小于或者多于n个引脚。

公开(公告)号：WO1997044905A1

公开(公告)日：1997-11-27

申请号：PCT/US1997008186

申请日：1997-05-21

Applicant: MICROCHIP TECHNOLOGY, INC.

Inventor： MICROCHIP TECHNOLOGY, INC. ,  HULL, Richard, L. ,  BINGHAM, Gregory ,  FINK, Scott ,  ROGERS, James, Clark ,  ELLISON, Scott

IPC: H03L07/00

CPC classification number: G06F15/7814

Abstract: The present invention relates to a microcontroller that may be configured to operate without the accompaniment of any external component. The microcontroller can function in a proper manner from the application of only power and signal lines with no external component required. The microcontroller (10) has integrated internal reset (14) and oscillator (16) circuitry into the microcontroller. The microcontroller has also integrated simple external components such as current limiting resistors into the microcontroller.

Abstract translation: 本发明涉及一种微控制器，其可被配置为在没有任何外部部件的伴随的情况下运行。 只有电源和信号线的应用，微控制器才能正常工作，无需外部元件。 微控制器（10）将内部复位（14）和振荡器（16）电路集成到微控制器中。 微控制器还将简单的外部元件（如限流电阻）集成到微控制器中。

公开(公告)号：WO2022256220A1

公开(公告)日：2022-12-08

申请号：PCT/US2022/031068

申请日：2022-05-26

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： GRAUMANN, Peter John Waldemar

IPC: G06F11/10

Abstract: A method for memory protection includes receiving a burst-write instruction that includes data and a burst-write address. The data are segmented into a plurality of data blocks. One or more bits of the burst-write address, or a hash of the burst-write address are concatenated to respective data blocks to obtain data-and-write-address-bit (DWAB) segments. A SECDED ECC is executed on respective DWAB segments to generate a corresponding plurality of sets of parity bits (DWAB-PB). Respective DWAB-PB are concatenated to the corresponding data block to generate corresponding forward-error-correction (FEC) blocks, none of the FEC blocks including the burst-write address or the hash of the burst-write address. A burst-write command and a respective portion of a respective FEC block is sent to respective memory devices during a plurality of beats until all of the beats of the burst-write have been sent.

公开(公告)号：WO2022250741A1

公开(公告)日：2022-12-01

申请号：PCT/US2022/011036

申请日：2022-01-03

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： ZUOLO, Lorenzo ,  MICHELONI, Rino

IPC: G11C29/44 ,  G11C29/02 ,  G11C29/50 ,  G11C16/34 ,  G06N3/08

Abstract: A method for outlier management at a flash controller includes testing a flash memory device to identify one or more outlier blocks of the flash memory device. Hyperparameters for a DNN are loaded into a training circuit. Test reads of the one or more outlier blocks are performed and a number of errors in the test reads is identified. The DNN is trained using a mini-batch training process and using the identified number of errors in the test reads and is tested to determine whether the trained DNN meets a training error threshold. The performing, the identifying, the training and the testing are repeated until the trained DNN meets the training error threshold to identify parameters of an outlier-block DNN. A neural network operation is performed using the identified parameters to predict a set of TVSO values. A read is performed using the set of predicted TVSO values.

公开(公告)号：WO2022250722A1

公开(公告)日：2022-12-01

申请号：PCT/US2021/053276

申请日：2021-10-02

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： MICHELONI, Rino ,  ZUOLO, Lorenzo

IPC: G11C11/56 ,  G11C16/26 ,  G11C16/34 ,  G11C29/02 ,  G06N3/02

Abstract: A method for performing a read of a flash memory includes storing configuration files for a plurality of RRD-compensating RNNs. A current number of PE cycles for a flash memory are identified and TVSO values are identified corresponding to the current number of PE cycles. A current retention time and a current number of read disturbs for the flash memory are identified. The configuration file of the RRD-compensating RNN corresponding to the current number of PE cycles, the current retention time and current number of read disturbs is selected and is loaded into a neural network engine to form an RNN core in the neural network engine. A neural network operation of the RNN core is performed to predict RRD-compensated TVSO values. The input to the neural network operation includes the identified TVSO values. A read of the flash memory is performed using the predicted RRD-compensated TVSO values.

公开(公告)号：WO2022231649A1

公开(公告)日：2022-11-03

申请号：PCT/US2021/053284

申请日：2021-10-03

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： NORRIE, Christopher I. W.

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38

Abstract: In one implementation devoid of an effective address generator a method of call operation comprises pushing one or more parameters onto a first stack, pushing the contents of one or more registers onto a second stack, popping off the first stack one or more of the parameters into one or more of the registers whose contents were pushed onto the second stack, performing register to register operations on the one or more registers whose contents were pushed onto the second stack with a result of the register to register operations being stored in a result register, the result register being one of the one or more registers whose contents were pushed onto the second stack, popping off the second stack the contents of all the one or more registers into their respective registers from which they came, and returning control to an instruction following the call.

公开(公告)号：WO2022197325A1

公开(公告)日：2022-09-22

申请号：PCT/US2021/053281

申请日：2021-10-03

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： DONTHU, Sathishkumar ,  REDDY, Battu Prakash

IPC: G06F17/15 ,  G06N3/063

Abstract: A method and apparatus for performing a convolution of a NxN matrix. A weights matrix for a NxN Convolutional Neural Network (CNN) is received and is divided into 3x3 weights matrixes. Lines of image values are read and are stored in a buffer as sets of image values. A 3x3 convolution is performed to generate a 3x3 convolution value. All 3x3 convolution values associated with a particular NxN convolution and a particular set of image values are summed. The 3x3 convolutions and the summing are repeated until all columns in the set of image values have been processed; and the reading, the storing, the performing 3x3 convolutions, the summing and the repeating performing 3x3 convolutions are repeated until all lines of image values have been processed. The sums associated with a particular NxN convolution are added together to generate an NxN convolution value for each of the NxN convolutions.

公开(公告)号：WO2022039780A1

公开(公告)日：2022-02-24

申请号：PCT/US2021/013738

申请日：2021-01-15

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： ZUOLO, Lorenzo ,  MICHELONI, Rino

IPC: G06N3/04 ,  G06N3/08 ,  G11C16/00

Abstract: A method includes storing configuration files of a Multi-Core Neural Network Inference (MCNNI) model having Independent Categorized-Core-Portions (ICCP's). Each ICCP corresponds to one of a plurality of categories for each parameter. A first plurality of weighting values on each row of the weighting matrix of the MCNNI model have a nonzero value and a second plurality of weighting values on each row having a value of zero. The configuration files are loaded into a neural network engine. The operation of the integrated circuit device is monitored to identify a usage value corresponding to each of the parameters. A single neural network operation is performed using the usage values as input to generate, at the output neurons of each ICCP, output values indicating an estimation of one or more variable. The output values of the ICCP that corresponds to the input usage values are identified and are sent as output.