公开(公告)号：WO2022231733A1

公开(公告)日：2022-11-03

申请号：PCT/US2022/021525

申请日：2022-03-23

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： NORRIE, Christopher I. W.

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38

Abstract: In one implementation a vector processor unit having preload registers for at least some of vector length, vector constant, vector address, and vector stride. Each preload register has an input and an output. All the preload register inputs are coupled to receive a new vector parameters. Each of the preload registers' outputs are coupled to a first input of a respective multiplexor, and the second input of all the respective multiplexors are coupled to the new vector parameters.

公开(公告)号：WO2022231649A1

公开(公告)日：2022-11-03

申请号：PCT/US2021/053284

申请日：2021-10-03

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： NORRIE, Christopher I. W.

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38

Abstract: In one implementation devoid of an effective address generator a method of call operation comprises pushing one or more parameters onto a first stack, pushing the contents of one or more registers onto a second stack, popping off the first stack one or more of the parameters into one or more of the registers whose contents were pushed onto the second stack, performing register to register operations on the one or more registers whose contents were pushed onto the second stack with a result of the register to register operations being stored in a result register, the result register being one of the one or more registers whose contents were pushed onto the second stack, popping off the second stack the contents of all the one or more registers into their respective registers from which they came, and returning control to an instruction following the call.