公开(公告)号：EP0426623B1

公开(公告)日：1996-01-10

申请号：EP90830469.4

申请日：1990-10-22

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Dell'Oro, Annalisa ,  Corazzo, Fulvio ,  Tognini, Pietro ,  Conegian, Stefano

IPC: H04Q11/04

CPC classification number: H04Q11/0471 ,  H04Q2213/13174 ,  H04Q2213/13199 ,  H04Q2213/13209 ,  H04Q2213/13214 ,  H04Q2213/13216 ,  H04Q2213/13297 ,  H04Q2213/13305 ,  H04Q2213/1331 ,  H04Q2213/1332 ,  H04Q2213/13322 ,  H04Q2213/1336 ,  H04Q2213/13361 ,  H04Q2213/13362

公开(公告)号：EP0690562A1

公开(公告)日：1996-01-03

申请号：EP94830324.3

申请日：1994-06-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Rezzi, Francesco ,  Baschirotto, Andrea ,  Castello, Rinaldo

IPC: H03F3/45 ,  H03H11/04

CPC classification number: H03F3/45076 ,  H03F2200/261 ,  H03H11/0433

Abstract: The invention relates to a transconductor circuit with a differential input and a single output, comprising two input transistors (M1, M2) whose primary conduction terminals (D1, S1, D2, S2) are respectively connected together; in this way, variations in load current and voltage can be made lower, thereby also lowering distortion from changes in their transconductance.

Abstract translation: 本发明涉及一种具有差分输入和单输出的跨导电路，包括其一次导通端子（D1，S1，D2，S2）分别连接在一起的两个输入晶体管（M1，M2） 以这种方式，可以降低负载电流和电压的变化，从而也降低其跨导变化的变形。 $$

公开(公告)号：EP0686978A1

公开(公告)日：1995-12-13

申请号：EP94830276.5

申请日：1994-06-07

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Mazzali, Stefano

IPC: G11C29/00 ,  G06F11/20

CPC classification number: G11C29/82 ,  G11C29/10 ,  G11C29/24 ,  G11C29/52

Abstract: A method for in-factory testing of a flash EEPROM device comprising a matrix of memory cells (1) and redundancy memory cells (1') for functionally substituting defective memory cells (1''), comprises the steps of: programming all the memory cells (1) of the memory device; submitting all the memory cells (1) of the memory device to a preliminary electrical erasure for a time much shorter than an average erasing time of the memory cells (1); reading the information stored in all the memory cells (1) of the memory device; memorizing the addresses of defective memory cells (1'') which have been read as erased memory cell; storing the addresses of the defective memory cells (1'') in redundancy registers (15,20) associated to redundancy memory cells (1') which must substitute the defective memory cells (1'').

Abstract translation: 一种用于在工厂内测试闪存EEPROM器件的方法，包括用于功能代替有缺陷的存储器单元（1“）的存储器单元（1）和冗余存储器单元（1'）的矩阵，包括以下步骤：对所有存储器 存储器件的单元（1）; 将所述存储器件的所有存储器单元（1）提交到比所述存储器单元（1）的平均擦除时间短得多的时间内的初步电擦除; 读取存储在所述存储器装置的所有存储单元（1）中的信息; 存储读取为被擦除的存储单元的有缺陷的存储单元（1“）的地址; 将有缺陷的存储器单元（1“）的地址存储在冗余存储器单元（1'）中的冗余寄存器（15,20）中，所述冗余存储器单元必须替代有缺陷的存储器单元（1”）。

公开(公告)号：EP0685921A1

公开(公告)日：1995-12-06

申请号：EP94830272.4

申请日：1994-05-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Rossi, Domenico ,  Tahara, Hisashi

IPC: H02M3/07

CPC classification number: H02M3/07

Abstract: A BiCMOS capacitive charge pump circuit for low supply voltage has a bipolar part, functionally reproducing a basic charge pump circuit and a CMOS part that comprises MOS transistors (M1, M2) functionally connected in parallel with the driving switch toward ground potential (T3) of the charge transfer capacitance (C1) and in parallel with the output diode (T7) for substantially nullifying voltage drops on the respective bipolar components (T3, T7). A special driving circuit (T8, R2, I2), powered at the boosted output voltage (V OUT ) responds to the rise of the voltage on the output node above a minimum level, as ensured by the bipolar part of the charge pump circuit, to drive said MOS transistors (M1, M2), thus allowing the output voltage to reach a level that is substantially double the supply voltage (Vs), also when the latter is exceptionally low for reliably ensuring switching of the CMOS part of the circuit.

Abstract translation: 用于低电源电压的BiCMOS电容电荷泵电路具有双极性部分，功能上再现基本电荷泵电路和CMOS部件，其包括与驱动开关并联连接到地电位（T3）的MOS晶体管（M1，M2） 电荷转移电容（C1）并且与输出二极管（T7）并联，用于基本上消除各个双极组件（T3，T7）上的电压降。 在升压输出电压（VOUT）下供电的特殊驱动电路（T8，R2，I2）响应于输出节点上的电压上升到最低电平以上，由电荷泵电路的双极部分确保， 驱动所述MOS晶体管（M1，M2），从而允许输出电压达到基本上是电源电压（Vs）的两倍的水平，而且当输出电压非常低时，可靠地确保电路的CMOS部分的切换。

公开(公告)号：EP0580919B1

公开(公告)日：1995-12-06

申请号：EP92830418.7

申请日：1992-07-28

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Ferrario, Bruno

IPC: H02M3/156

CPC classification number: H02M1/4225 ,  H03K7/06 ,  Y02B70/126

公开(公告)号：EP0681362A1

公开(公告)日：1995-11-08

申请号：EP94830217.9

申请日：1994-05-06

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Pedrazzini, Giorgio ,  Scrocchi, Giuseppe ,  Cordini, Paolo ,  Rossi, Domenico

IPC: H02M3/156

CPC classification number: H02M3/156 ,  H02M3/1563

Abstract: A fully digital, current mode, PWM control is realized by employing two distinct comparators (COMP1,COMP2), both reading the voltage drop on a sensing resistance (Rsense). The first comparator (COMP1) exerts an open-loop current mode control. The second comparator (COMP2), establishing a second higher current threshold than the current threshold set by the first comparator (COMP1), triggers a disabling circuit of the output power transistor for a preset period of time, when the current level through the output stage uncontrollably rises beyond the second threshold. This may occur because of an insufficient discharge from the load circuit inductance (L) during off-phases of the output power transistor of the extra energy stored during switching delay periods of the first (open loop control) comparator (COMP1).
The frequency of the sequence of bursts may be precisely controlled to be well outside the frequency range of interest to prevent disturbances.

Abstract translation: 通过采用两个不同的比较器（COMP1，COMP2）实现全数字电流模式，PWM控制既可读取感测电阻（Rsense）上的电压降。 第一个比较器（COMP1）进行开环电流模式控制。 建立比由第一比较器（COMP1）设置的电流阈值的第二高电流阈值的第二比较器（COMP2）在预设时间段内触发输出功率晶体管的禁用电路，当通过输出级的电流电平 不可控地超过第二个门槛。 这可能是由于在第一（开环控制）比较器（COMP1）的开关延迟时段期间存储的额外能量的输出功率晶体管的非相位期间来自负载电路电感（L）的放电不足。 突发序列的频率可以被精确地控制在很好的在感兴趣的频率范围之外，以防止干扰。

公开(公告)号：EP0678909A1

公开(公告)日：1995-10-25

申请号：EP94830187.4

申请日：1994-04-20

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Maccagno, Pierre

IPC: H01L21/66

CPC classification number: H01L22/34 ,  H01L22/12 ,  H01L22/14

Abstract: RF plasma-induced potentials on relatively thin gate dielectric layers capable of conducting by a Fowler-Nordheim mechanism may be accurately determined by employing as potential sensing structure an EEPROM cell having its control gate capacitively coupled to the substrate through a gate dielectric layer which reproduces the condition of an intervening discharge through a Fowler-Nordheim current. The connection is interrupted by a polyfuse before measuring the threshold voltage of the sensing EEPROM cell. The measured peak potential values induced by the plasma depend on the thickness of the gate dielectric layer, as they will be on production wafers. The normalization of the "antenna" area of the sensing structures will permit to precisely evaluate the electrical stress induced by the plasma on sensitive integrated structures.

Abstract translation: 可以通过采用作为电位感测结构的EEPROM感应结构来准确地确定在能够通过Fowler-Nordheim机制导通的相对薄的栅极电介质层上的RF等离子体感应电位，其中EEPROM单元的控制栅极通过栅介质层电容耦合到衬底，栅极电介质层再现 通过福勒 - 诺德海姆（Fowler-Nordheim）电流进行中间放电的条件。 在测量感测EEPROM单元的阈值电压之前，该连接被多熔丝中断。 由等离子体引起的测量的峰值电位值取决于栅极电介质层的厚度，因为它们将在生产晶片上。 感测结构的“天线”区域的归一化将允许精确评估等离子体在敏感的一体化结构上引起的电应力。

公开(公告)号：EP0676768A1

公开(公告)日：1995-10-11

申请号：EP94830143.7

申请日：1994-03-28

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Campardo, Giovanni ,  Dallabora, Marco

IPC: G11C16/06

CPC classification number: G11C16/3445 ,  G11C16/28 ,  G11C16/344

Abstract: To reduce the supply voltage (V CC ) of a nonvolatile memory (48), a read reference signal (H) is generated having a reference threshold value ranging between the maximum permissible threshold value for erased cells and the minimum permissible threshold value for written cells. To avoid reducing the maximum supply voltage, the characteristic (H) of the read reference signal is composed of two portions: a first portion (H1), ranging between the threshold value and a predetermined value (V s ), presents a slope lower than that of the characteristic (A, G) of the memory cells (50); and a second portion (H2), as of the predetermined value of the supply voltage, presents the same slope as the memory cells. The shifted-threshold, two-slope characteristic is achieved by means of virgin cells (11-13) so biased as to see bias voltages lower than the supply voltage.

Abstract translation: 为了减少非易失性存储器（48）的电源电压（VCC），则生成读基准信号（H），具有用于擦除的单元的最大允许阈值和写入单元的最小可允许的阈值之间的范围内的基准的阈值。 为了避免降低所读取的参考信号被由两个部分组成的最大电源电压，特性（H）：第一部分（H1），所述阈值和预定值（VS）之间的范围内，呈现出斜率低于 的特性（A，G）的存储单元（50）; 和第二部分（H2），作为电源电压的规定值的，呈现相同的斜率的存储单元。 移位的阈值，双斜率特性由处女细胞（11-13），以便偏置为看偏置电压比电源电压低的来实现。

公开(公告)号：EP0675504A1

公开(公告)日：1995-10-04

申请号：EP94830156.9

申请日：1994-03-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Padoan, Silvia ,  Maccarrone, Marco ,  Olivo, Marco

IPC: G11C29/00 ,  G11C16/06

CPC classification number: G11C29/50004 ,  G06F2201/81 ,  G11C16/04 ,  G11C29/50

Abstract: A circuit device (1) for measuring the threshold voltage distribution among electrically programmable, non-volatile memory cells, which device comprises a differential amplifier (3) having a first input connected to a first circuit leg including at least one memory cell (2) and a second input connected to a second or reference circuit leg (4), and circuit means effective to cause an unbalance in the values of the currents flowing in the reference leg. The device is connected between a first supply voltage (Vdd) reference and a second voltage reference (GND), and said circuit means comprise a generator of a varying current as a function of the supply voltage (Vdd) which is associated with the reference leg (4).

Abstract translation: 一种电路装置（1），用于测量电可编程，非易失性存储器单元中的阈值电压分布，该装置包括（3），其具有连接到第一电路支路的第一输入包括至少一个存储单元中的差分放大器（2） 和第二输入连接到第二或参考电路腿（4），和电路装置有效地使在参考腿中流动的电流的值，以不平衡。该装置连接在第一电源电压（VDD）参考和之间 第二电压基准（GND），并且所述电路装置包括一个变化的电流的发生器作为与基准支柱（4）相关联的电源电压（Vdd）的所有的功能。

公开(公告)号：EP0367006B1

公开(公告)日：1995-09-27

申请号：EP89119160.3

申请日：1989-10-16

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Barsanti, Andrea ,  Diazzi, Claudio ,  Vio, Fabio

IPC: H03K17/06

CPC classification number: H03K17/063